About

Anant Agarwal is a faculty member at the Massachusetts Institute of Technology (MIT) in the Department of Electrical Engineering and Computer Science (EECS). He serves as the CEO of edX and holds a position as a Professor in the department. His research areas include Computer Architecture, Programming Languages and Software Engineering, and Systems and Networking. His work involves designing systems that sense, process, and transmit energy and information, leveraging computational, theoretical, and experimental tools to develop groundbreaking sensors, energy transducers, and physical substrates for computation. Agarwal's contributions focus on addressing shared challenges facing humanity through innovative system development and research in electrical engineering and computer science.

Research topics

• Electrical engineering
• Optoelectronics
• Materials science
• Quantum mechanics
• Physics
• Engineering
• Chemistry

Selected publications

• Switching Loss Characterization with Uncertainty Quantification for 3.3 kV Monolithic Versus Discrete SiC Bidirectional FETs

  2026-03-22

  article

  This work presents a systematic investigation into the switching losses of 3.3 kV SiC bidirectional field-effect transistors (BiDFETs) in common-drain configuration. Hard-switching characterization is performed at 2 kV bus voltage, 5–20 A load currents, and 30–150°C case temperatures. The first quantitative comparison between monolithic and discrete (two-chip) architectures reveals that monolithic integration exhibits higher switching losses due to tighter capacitive coupling. Gate drive configuration impact is also quantified: turn-on energy exhibits negligible sensitivity to single- versus dual-gate driving, while turn-off energy shows measurable reduction under dual-gate operation due to reduced body diode reverse recovery. These findings are enabled by a power-based integration framework with uncertainty quantification, which maintains measurement confidence in the presence of post-switching oscillations extending beyond standard IEC 60747-8 windows. The results provide foundational switching characteristics and architecture selection guidelines for medium-voltage SiC BiDFET implementation in circuits.

  PublisherDOI

• Technique for the Accurate Measurement of Average dv/dt of SiC MOSFET

  2026-03-22

  articleSenior author

  SiC MOSFETs are known to exhibit high dv/dt during switching transitions. While this lowers the switching loss, a high dv/dt is reported to cause degradation of electrical components such as the insulation in motor windings. To mitigate such issues, various power electronic applications require the average dv/dt to be limited to a prescribed value. Also, the magnitude of dv/dt is reported to change dynamically with a change in operating conditions such as drain-source voltage, device current, and its junction temperature. Hence, an accurate feedback of dv/dt is required to enable its effective regulation. Existing methods have suggested using a high-speed analog-to-digital converter (ADC) to achieve the same, as the switching transition time is in the order of nanoseconds. However, this increases implementation costs. To address the aforementioned challenge, this manuscript first mathematically examines the response of the feedback network during a drain-source voltage transition. Based on the same, the parameters correlated to the average dv/dt are identified. Next, a measurement technique is proposed which enables the use of a conventional (low-cost) ADC to sample the identified parameters and accurately measure the average dv/dt. Further, a measurement circuit is proposed to implement the proposed technique. Finally, an experimental investigation is conducted under various operating conditions to validate the proposed technique. An accuracy of over 92% is achieved in the measured value of average dv/dt.

  PublisherDOI

• Artificial Neural Network-Based Screening Method for Short-Circuit Withstand Time in Packaged SiC MOSFETs to Enhance Device Consistency

  IEEE Electron Device Letters · 2025-04-21 · 3 citations

  articleSenior author

  Developing an effective methodology to enhance the uniformity of short-circuit withstand time (SCWT) in silicon carbide (SiC) MOSFETs is crucial for ensuring device reliability and consistency in power electronic systems. This letter presents a detailed analysis of SCWT variations caused by inevitable process-induced deviations and introduces a new screening approach based on artificial neural network (ANN) technology. A two-hidden-layer ANN model is constructed using characteristic parameters extracted from SiC MOSFETs. The trained model accurately predicts the SCWT of TCAD-simulated SiC MOSFETs, achieving a maximum error of less than 15% and an average error of only 2%. This proposed method effectively identifies and removes devices with shorter SCWT without compromising the performance of reliable devices, thereby enhancing post-fabrication consistency for packaged devices.

  PublisherDOI

• Short Circuit Withstand Time Screening of 1.2 kV Commercial SiC MOSFETs: A Non-Destructive Approach

  Electronics · 2025-07-10 · 3 citations

  articleOpen accessSenior author

  SiC MOSFETs are becoming increasingly popular due to their superior material properties, but they lack the required reliability and ruggedness for safe applications. One of the biggest challenges in short-circuit (SC) reliability of the commercial devices and hence in the SC protection circuit design is the variability of SC withstand time (SCWT) among the devices from the same vendor, even with the same lot and batch number. In this work, a novel SC screening methodology has been presented to remove devices with lower SCWT from a pool of devices without damaging the reliable ones. The SC screening methodology has been developed using Sentaurus TCAD simulation, which is further verified using commercial devices. This work can potentially reduce field failure and, as a result, can enhance the reliability of the SiC MOSFETs in real-world applications.

  PublisherOA PDFDOI

• Frameworks for Data Management in Modern Enterprises: Enhancing Predictive Analytics and Process Optimization

  Lecture notes in networks and systems · 2025-01-01

  book-chapter1st authorCorresponding
  PublisherDOI

• TRANSFORMING CUSTOMER EXPERIENCE THROUGH NLP AND SENTIMENT ANALYSIS

  International Journal of Data Mining & Knowledge Management Process · 2025-05-02

  articleOpen accessSenior author

  The integration of Sentiment Analysis (SA) and Natural Language Processing (NLP) assists companies in improving customer service by examining actionable insights from unstructured data sources like social media tweets and customer reviews. RoBERTa acts as a sophisticated transformer-based model that is capable of analyzing complex customer sentiment data. This paper assesses the performance of RoBERTa for sentiment classification while investigating solutions to class imbalance issues, sarcasm detection difficulties, and ethical issues. The discussion proposes optimization techniques for RoBERTa on different data sets to register high accuracy and outline future research directions to improve fairness and explainability. The paper concludes its material by introducing mathematical frameworks as performance metric tools in addition to optimization and evaluation procedures.

  PublisherDOI

• A Hybrid Multilevel Converter-Based High-Gain Isolated DC/DC Converter for Grid-Tied Energy Storage Applications

  2025-03-16

  articleSenior author

  A 7 kV/400 V isolated DC-DC converter utilizing 6.5 kV and 3.3 kV SiC MOSFETs is proposed for medium-voltage energy storage systems. The topology integrates a switched capacitor (SC) stage with modular multilevel converter (MMC) structure, achieving 12:1 voltage step-down before transformer isolation. The SC stage operates at 1 kHz with 6.5 kV devices, while MMC submodules switch at 20 kHz using 3.3 kV devices, enabling 40 kHz transformer operation through frequency multiplication. Capacitor voltage self-balancing is achieved through a novel switching scheme, and power flow is regulated through phase-shift control between primary and secondary voltages of transformer. Zero-voltage switching is realized for MMC sub-modules during voltage transitions. Simulation results validate the design, and experimental characterization of SiC devices demonstrates switching performance with dv/dt up to 40 V/ns.

  PublisherDOI

• THE VANISHING HERITAGE OF AGRA, INDIA THE SALE OF THE TAJ MAHAL

  Journal of the Pakistan Historical Society · 2025-06-30

  articleOpen access1st authorCorresponding

  This paper analyses the systematic obliteration of Mughul architectural heritage in Agra during the governance of the British East India Company from 1803 to 1858. It highlights the pronounced disparity between the conservation of Mughul monuments in Delhi and their extensive destruction in Agra. The study demonstrates that numerous palaces, gardens, tombs, and other edifices were demolished, sold, or repurposed, thereby obliterating centuries of cultural heritage. Notable instances comprise the auction of the Taj Mahal, the transformation of Akbar's tomb into an orphanage, and the significant devastation within Agra Fort. The paper argues that this deliberate erasure of Mughul culture was part of a British policy to establish dominance, facilitated by the severance of emotional bonds between the local population and their heritage. It concludes by emphasising the significance of historical knowledge and cultural preservation in sustaining national identity and advocates for a revitalised emphasis on protecting Indo- Muslim architectural heritage.

  PublisherOA PDFDOI

• Investigation of Screening Methods for 1.2 kV 4H-SiC MOSFETs Using High Gate Voltage Pulses and Unclampled Inductive Switching

  2025-03-30

  articleSenior author

  This study investigates the effectiveness of high gate voltage pulse (HVP) stress and unclamped inductive switching (UIS) tests in screening out infant gate oxide failures in 1.2 kV SiC MOSFETs. Foundry-fabricated pristine devices were systematically tested using HVP and UIS screening conditions at room temperature. Short-duration high gate voltage stress proved effective in identifying infant failures. Analysis of screening results from over 4,000 devices revealed a strong correlation between screening rates and drain leakage, suggesting that stringent drain leakage criteria can help rule out potentially weak devices.

  PublisherDOI

• Implementation of WBG devices in circuits - Electric Drive Technologies Project (Final Technical Report)

  2025-06-03

  report
  PublisherDOI

Frequent coauthors

• John W. Palmour

  Wolfram Research (United States)

  167 shared

• Sei‐Hyung Ryu

  122 shared

• Charles Scozzie

  71 shared

• M. E. Levinshteĭn

  60 shared

• Sumi Krishnaswami

  Cree (China)

  54 shared

• Craig Capell

  Cree (China)

  45 shared

• Mrinal K. Das

  University of Leicester

  44 shared

• Henry Hoffmann

  University of Chicago

  42 shared

Education

• Ph.D., Electrical Engineering and Computer Science

  Massachusetts Institute of Technology

  1989

• M.S., Electrical Engineering and Computer Science

  Massachusetts Institute of Technology

  1985

• B.S., Electrical Engineering

  University of Pune

  1981