About

Jessica Swanston Baker is an associate professor in the Department of Music at the University of Chicago and serves as the Director of Graduate Studies. She is an ethnomusicologist specializing in contemporary popular music of and in the Circum-Caribbean. Her research and critical interests include tempo and aesthetics, coloniality, decolonization, and race/gender and respectability. As a Caribbeanist, her work focuses on issues within Caribbean theory related to small islands-nations, such as representation and invisibility, vulnerability, and sovereignty. Her current ethnographic book project, Island Time: Speed and the Archipelago from St. Kitts and Nevis, examines the relationship between tempo perception and the gendered and raced legacies of colonization. Through historical and ethnographic analysis of colloquialisms and music reception, she explores how colonial understandings of black femininity and Enlightenment notions of musicianship influence perceptions of local music styles, such as wylers, as “too fast.” Her research also includes music tourism, particularly black diasporic travel between the United States and the Caribbean, and the performance and consumption of American soul music within Caribbean music festivals. Jessica holds a PhD in ethnomusicology from the University of Pennsylvania and a BM in Vocal Performance from Bucknell University. Prior to her appointment at Chicago, she was a postdoctoral fellow in Critical Caribbean Studies at Rutgers University.

Research topics

• Computer Science
• Quantum mechanics
• Physics
• Theoretical computer science
• Telecommunications
• Computer network
• Engineering
• Mathematics
• Algorithm
• Electronic engineering
• Distributed computing

Selected publications

• ReloQate: Transient Drift Detection and In-Situ Recalibration in Surface Code Quantum Error Correction

  ArXiv.org · 2026-02-28

  articleOpen accessSenior author

  Quantum error correction (QEC) promises to exponentially suppress qubit noise, but typically assumes spatially-uniform and temporally-constant noise rates. However, real quantum hardware exhibits variation in noise levels over time, which will be amplified by QEC if not addressed. To mitigate this drift in error rates, we leverage transient information readily available in surface code quantum error correction to predict logical error rates (LER) in real time. We infer a prediction model by sampling physical error rates from real hardware, and mapping detector fire rate (DFR), or parity of stabilizer measurements across QEC rounds, to LER. This allows for on-the-fly LER predictions without the typical characterization overhead required to determine LER. This method can easily be extended to other stabilizer codes. Importantly, we observe that this prediction should be accurate yet conservative (i.e. give an upper estimate) to enable appropriately fast responses to real-time physical error changes. That is, responses should be executed marginally ahead of time to allow for their execution to complete, and minimize time spent (ideally none) above intolerable error rates. More importantly, we pair this predictor with a scheme which remaps drifted logical qubits to fresh tiles in a patch-based architecture while their original tiles are recalibrated. Our results demonstrate DFR-based prediction to be an effective LER predictor, and remapping as a spatially efficient and timely mitigation response for small code distances, both of which are significant steps in furthering practical QEC.

  PublisherOA PDF

• Optimizing Logical Mappings for Quantum Low-Density Parity Check Codes

  ArXiv.org · 2026-03-17

  articleOpen accessSenior author

  Early demonstrations of fault tolerant quantum systems have paved the way for logical-level compilation. For fault-tolerant applications to succeed, execution must finish with a low total program error rate (i.e., a low program failure rate). In this work, we study a promising candidate for future fault-tolerant architectures with low spatial overhead: the Gross code. Compilation for the Gross code entails compiling to Pauli Based Computation and then reducing the rotations and measurements to the Bicycle ISA. Depending on the configuration of modules and the placement of code modules on hardware, one can reduce the amount of resulting Bicycle instructions to produce a lower overall error rate. We find that NISQ-based, and existing FTQC mappers are insufficient for mapping logical qubits on Gross code architectures because 1. they do not account for the two-level nature of the logical qubit mapping problem, which separates into code modules with distinct measurements, and 2. they naively account only for length two interactions, whereas Pauli-Products are up to length $n$, where $n$ is the number of logical qubits in the circuit. For these reasons, we introduce a two-stage pipeline that first uses hypergraph partitioning to create in-module clusters, and then executes a priority-based algorithm to efficiently assign clusters onto hardware. We find that our mapping policy reduces the error contribution from inter-module measurements, the largest source of error in the Gross Code, by up to $\sim36\%$ in the best case, with an average reduction of $\sim13\%$. On average, we reduce the failure rates from inter-module measurements by $\sim22\%$ with localized factory availability, and by $\sim17\%$ on grid architectures, allowing hardware developers to be less constrained in developing scalable fault tolerant systems due to software driven reductions in program failure rates.

  PublisherOA PDF

• INJEQT: Improved Magic-State Injection Protocol for Fault-Tolerant Quantum Extractor Architectures

  arXiv (Cornell University) · 2026-04-28

  preprintOpen accessSenior author

  Near-term FTQC system designs are constrained by limited error budgets and largely sequential execution of non-Clifford gates. As a result, reducing the number of the most-error prone instructions becomes critical for successful program execution. In this work, we study the extractor architecture, a recently proposed FTQC design that enables universal quantum computation on spatially-efficient QEC codes such as the BB code family. In these architectures, over $90\%$ of the total program error arises from the synthillation process, which involves $\lvert T\rangle$-state preparation and injection to implement non-Clifford gates. We observe that standard Rz synthillation requires multiple sequential $\lvert T\rangle$-state injections, each incurring an inter-module measurements, the most expensive instruction in the architecture, which cumulatively dominate the overall error budget. To address this bottleneck, we propose INJEQT, a $2$-factory design that uses an auxiliary code capable of synthesizing $Rz(θ)$ states with lower error rates. These states are then injected into the extractor modules using only a constant number of inter-module measurements. This approach reduces overall error rates by up to $22\times$. We further reduce the time overhead by a pre-fetching strategy that prepares the Rz states and their correction states in parallel. This approach improves the wall-clock time by up to $13\times$ and reduces the space-time cost by up to $7.2\times$, for an optimal choice of the number of INJEQT factories for each metric. We evaluate INJEQT for multiple state preparation techniques such as distillation, cultivation and STAR, and model the execution times for both lattice surgery-based and transversal CNOT based injections. Our results demonstrate that INJEQT is robust across factory choices and device technologies, enabling more efficient architectural designs for FTQC.

  PublisherDOI

• Optimizing Logical Mappings for Quantum Low-Density Parity Check Codes

  arXiv (Cornell University) · 2026-03-17

  preprintOpen accessSenior author

  Early demonstrations of fault tolerant quantum systems have paved the way for logical-level compilation. For fault-tolerant applications to succeed, execution must finish with a low total program error rate (i.e., a low program failure rate). In this work, we study a promising candidate for future fault-tolerant architectures with low spatial overhead: the Gross code. Compilation for the Gross code entails compiling to Pauli Based Computation and then reducing the rotations and measurements to the Bicycle ISA. Depending on the configuration of modules and the placement of code modules on hardware, one can reduce the amount of resulting Bicycle instructions to produce a lower overall error rate. We find that NISQ-based, and existing FTQC mappers are insufficient for mapping logical qubits on Gross code architectures because 1. they do not account for the two-level nature of the logical qubit mapping problem, which separates into code modules with distinct measurements, and 2. they naively account only for length two interactions, whereas Pauli-Products are up to length $n$, where $n$ is the number of logical qubits in the circuit. For these reasons, we introduce a two-stage pipeline that first uses hypergraph partitioning to create in-module clusters, and then executes a priority-based algorithm to efficiently assign clusters onto hardware. We find that our mapping policy reduces the error contribution from inter-module measurements, the largest source of error in the Gross Code, by up to $\sim36\%$ in the best case, with an average reduction of $\sim13\%$. On average, we reduce the failure rates from inter-module measurements by $\sim22\%$ with localized factory availability, and by $\sim17\%$ on grid architectures, allowing hardware developers to be less constrained in developing scalable fault tolerant systems due to software driven reductions in program failure rates.

  PublisherDOI

• CQM: Cyclic Qubit Mappings

  arXiv (Cornell University) · 2026-02-23

  preprintOpen accessSenior author

  Quantum computers show promise to solve select problems otherwise intractable on classical computers. However, noisy intermediate-scale quantum (NISQ) era devices are currently prone to various sources of error. Quantum error correction (QEC) shows promise as a path towards fault tolerant quantum computing. Surface codes, in particular, have become ubiquitous throughout literature for their efficacy as a quantum error correcting code, and can execute quantum circuits via lattice surgery operations. Lattice surgery also allows for logical qubits to maneuver around the architecture, if there is space for it. Hardware used for near-term demonstrations have both spatially and temporally varying error results in logical qubits. By maneuvering logical qubits around the topology, an average logical error rate (LER) can be enforced. We propose cyclic qubit mappings (CQM), a dynamic remapping technique implemented during compilation to mitigate hardware heterogeneity by expanding and contracting logical qubits. In addition to LER averaging, CQM shows initial promise given it's minimal execution time overhead and effective resource utilization.

  PublisherDOI

• Abstract 5982: Eradicating metastatic cancers by targeting a major tumor vulnerability of the K-RAS pathway: Seven in absentia homolog (SIAH)

  Cancer Research · 2026-04-03

  article1st authorCorresponding

  Abstract Background: Persistent activation of the K-RAS pathway is multipotent: its downstream signaling networks promote tumorigenesis, drug resistance, relapse, and metastasis. Despite newly developed state-of-the-art therapies, none have yet to achieve durable antitumor efficacy. Seven in absentia homologues (SIAHs) are a conserved family of RING-domain E3 ubiquitin ligases that function as the most downstream signaling gatekeepers in the K-RAS pathway. Our preclinical studies demonstrated that SIAH inhibition leads to a tumor eradication phenotype of multiple stage IV human cancer cell lines both in vitro and in vivo. Aims: We propose SIAH is a major tumor vulnerability and actionable drug target for inhibiting K-RAS pathway activation. In this study, we aim to elucidate the molecular mechanisms underpinning the antitumor efficacy of our potent SIAH inhibitor, SIAH2 PD, as a new targeted therapy to achieve tumor eradication. Methods: Reverse phase protein arrays (RPPAs) and principal component analysis (PCA) were used to quantify statistically significant fold-changes of 294 signaling proteins and phospho-proteins in response to SIAH blockade in five stage IV cell lines. RPPAs were performed in triplicate on MiaPaCa, MDA-MB-231, MDA-MB-468, HeLa, and A459 cell lines in which SIAH2 PD expression was controlled by a doxycycline (DOX)-inducible Tet-ON/OFF system. Four experimental conditions were used: Tet-ON vector control cells without DOX (group A) and with DOX induction (group B); Tet-ON-SIAH2 PD experimental cells without DOX (group C) and with DOX induction (group D). The ratios of each group were calculated in a pairwise comparison after normalization to GAPDH as an internal control. To validate putative targets of interest, immunofluorescence (IF), flow cytometry (FC), and Western blots (WB) were performed on cells for group C and D at 3-, 5-, and 7-days post-DOX-induction. Adherent and single cell suspensions were used respectively for cell-based assays in biological triplicates and normalized to α-Tubulin. Target protein expression was quantified and validated, and statistical analyses were performed by one-way ANOVA and T-tests using GraphPad Prism software. Results: The altered expression of NFκB, Caspase-3, Caspase-7, Cofilin, and PARP in response to SIAH blockade were independently validated by RPPA, WB, FC, and IF, demonstrating the roles of heightened cellular stress, apoptosis, and dysfunctional DNA damage and repair pathways induced by SIAHloss of function as mechanistic, synergistic to kill cancer cells and prevent tumor growth. Conclusions: RPPA cancer pathway mapping provides invaluable molecular insights into cancer network rewiring in response to SIAH blockade, revealing a major tumor vulnerability. This study supports the design of anti-SIAH-based, anti-EGFR/K-RAS targeted therapies to control and eradicate incurable human cancers. Citation Format: Jonathan M. Baker, Emanuel Frank Petricoin, Julia Wulfkhule, Andrew Howell, Ashleigh Hannah, Amy H. Tang. Eradicating metastatic cancers by targeting a major tumor vulnerability of the K-RAS pathway: Seven in absentia homolog (SIAH) [abstract]. In: Proceedings of the American Association for Cancer Research Annual Meeting 2026; Part 1 (Regular Abstracts); 2026 Apr 17-22; San Diego, CA. Philadelphia (PA): AACR; Cancer Res 2026;86(7 Suppl):Abstract nr 5982.

  PublisherDOI

• INJEQT: Improved Magic-State Injection Protocol for Fault-Tolerant Quantum Extractor Architectures

  ArXiv.org · 2026-04-28

  articleOpen accessSenior author

  Near-term FTQC system designs are constrained by limited error budgets and largely sequential execution of non-Clifford gates. As a result, reducing the number of the most-error prone instructions becomes critical for successful program execution. In this work, we study the extractor architecture, a recently proposed FTQC design that enables universal quantum computation on spatially-efficient QEC codes such as the BB code family. In these architectures, over $90\%$ of the total program error arises from the synthillation process, which involves $\lvert T\rangle$-state preparation and injection to implement non-Clifford gates. We observe that standard Rz synthillation requires multiple sequential $\lvert T\rangle$-state injections, each incurring an inter-module measurements, the most expensive instruction in the architecture, which cumulatively dominate the overall error budget. To address this bottleneck, we propose INJEQT, a $2$-factory design that uses an auxiliary code capable of synthesizing $Rz(θ)$ states with lower error rates. These states are then injected into the extractor modules using only a constant number of inter-module measurements. This approach reduces overall error rates by up to $22\times$. We further reduce the time overhead by a pre-fetching strategy that prepares the Rz states and their correction states in parallel. This approach improves the wall-clock time by up to $13\times$ and reduces the space-time cost by up to $7.2\times$, for an optimal choice of the number of INJEQT factories for each metric. We evaluate INJEQT for multiple state preparation techniques such as distillation, cultivation and STAR, and model the execution times for both lattice surgery-based and transversal CNOT based injections. Our results demonstrate that INJEQT is robust across factory choices and device technologies, enabling more efficient architectural designs for FTQC.

  PublisherOA PDF

• Cyclone: Designing Efficient and Highly Parallel QCCD Architectural Codesigns for Fault Tolerant Quantum Memory

  2026-01-31

  articleSenior author

  Modular trapped-ion quantum computing hardware, known as Quantum Charge Coupled Devices (QCCDs) require shuttling operations in order to maintain effective all-to-all connectivity. Each module or trap can perform only one operation at a time, resulting in low intra-trap parallelism, but there is no restriction on operations happening on independent traps, enabling high inter-trap parallelism. Unlike their superconducting counterparts, the design space for QCCDs is relatively flexible and can be explored beyond the constraints of two-dimensional grids. In this work, we are motivated by the opportunity to explore the QCCD design space in the context of optimizing for non-topological CSS codes. In particular, current grid-based architectures significantly limit the performance of many promising, high-rate codes such as hypergraph product codes and bivariate bicycle codes. Many of these codes are highly parallelizable, meaning that with appropriate hardware layouts and matching software schedules, execution latency can be greatly reduced. Faster execution, in turn, reduces error accumulation from decoherence and heating, ultimately improving code performance when mapped to realistic hardware. However, current 2D grid designs suffer from numerous trap to trap “roadblocks”, forcing serialization and destroying the inherent parallelism of these codes. To address this, we propose Cyclone, a circular software-hardware codesign that departs from traditional 2D grids in favor of a flexible ring topology, where ancilla qubits move in lockstep. Cyclone eliminates roadblocks, bounds total movement, and enables high levels of parallelism, resulting in up to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4 \times$</tex> speedup in execution times. In addition to temporal efficiency, Cyclone also offers large spatial efficiency when compared to a grid codesign. It requires fewer traps, fewer junctions, and only a constant number of Digital-toAnalog Converters (DAC), as opposed to grid architectures, where DAC count scales linearly with the number of traps. With hypergraph product codes, Cyclone achieves up to a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2 \times$</tex> order of magnitude improvement in logical error rate, and with bivariate bicycle codes, this improvement reaches up to a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$3 \times$</tex> in order of magnitude. Spatially, Cyclone reduces the number of required traps and ancilla qubits by <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2 \times$</tex>. The overall spacetime improvement over a standard grid is up to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\sim 20 \times$</tex>, demonstrating Cyclone as a scalable and efficient alternative to conventional 2D QCCD architectures.

  PublisherDOI

• Price and Payoff: Non-Determinism in Fault Tolerant Quantum Computation

  ArXiv.org · 2026-05-08

  articleOpen accessSenior author

  A promising approach to achieving scalable fault-tolerant quantum computation is the use of quantum error correction (QEC) codes augmented with magic states i.e. resource states produced via distillation, cultivation, or $R_z$ synthesis and teleported into the circuit as needed. Because magic-state production dominates the space-time volume of fault-tolerant programs, system architects must decide how many production units to allocate. Current approaches rely on deterministic analysis that either provisions for worst-case peak demand (wasting valuable qubit resources on factories that are never simultaneously utilized) or assumes average demand, which increases execution time. In this work, we build a simulation framework that couples circuit scheduling with different stochastic magic state production models, and use it to quantify the impact of non-determinism on circuit execution. We show that non-determinism has a dual effect that deterministic models cannot capture: it inflates total execution time (the price), while deflating peak per-cycle resource demand (the payoff). For distillation-based architectures, this demand smoothing shifts the space-time-optimal provisioning point: fewer factories are needed to minimize space-time volume than deterministic analysis predicts. Across benchmarks, stochastic-aware provisioning reduces space-time volume by up to 27% compared to the deterministic optimum for distillation, while requiring up to 30% fewer factories. We characterize these effects across each preparation mechanism, map the resulting design-space tradeoffs, and demonstrate that static resource estimation systematically mis-characterizes the cost of fault-tolerant execution. Our results establish that stochastic-aware analysis is necessary for right-sizing the factory allocations and should replace deterministic heuristics as the standard methodology for FTQC resource planning.

  PublisherOA PDF

• Price and Payoff: Non-Determinism in Fault Tolerant Quantum Computation

  arXiv (Cornell University) · 2026-05-08

  preprintOpen accessSenior author

  A promising approach to achieving scalable fault-tolerant quantum computation is the use of quantum error correction (QEC) codes augmented with magic states i.e. resource states produced via distillation, cultivation, or $R_z$ synthesis and teleported into the circuit as needed. Because magic-state production dominates the space-time volume of fault-tolerant programs, system architects must decide how many production units to allocate. Current approaches rely on deterministic analysis that either provisions for worst-case peak demand (wasting valuable qubit resources on factories that are never simultaneously utilized) or assumes average demand, which increases execution time. In this work, we build a simulation framework that couples circuit scheduling with different stochastic magic state production models, and use it to quantify the impact of non-determinism on circuit execution. We show that non-determinism has a dual effect that deterministic models cannot capture: it inflates total execution time (the price), while deflating peak per-cycle resource demand (the payoff). For distillation-based architectures, this demand smoothing shifts the space-time-optimal provisioning point: fewer factories are needed to minimize space-time volume than deterministic analysis predicts. Across benchmarks, stochastic-aware provisioning reduces space-time volume by up to 27% compared to the deterministic optimum for distillation, while requiring up to 30% fewer factories. We characterize these effects across each preparation mechanism, map the resulting design-space tradeoffs, and demonstrate that static resource estimation systematically mis-characterizes the cost of fault-tolerant execution. Our results establish that stochastic-aware analysis is necessary for right-sizing the factory allocations and should replace deterministic heuristics as the standard methodology for FTQC resource planning.

  PublisherDOI

Frequent coauthors

• Frederic T. Chong

  University of Chicago

  79 shared

• Casey Duckering

  23 shared

• Kaitlin N. Smith

  19 shared

• Gokul Subramanian Ravi

  18 shared

• Andrew Litteken

  12 shared

• David I. Schuster

  11 shared

• David Schuster

  Electronics for Imaging (United States)

  11 shared

• Ali Javadi-Abhari

  11 shared

Awards & honors

• 2015-16 postdoctoral fellow in Critical Caribbean Studies at…