About

Aniket De is a historian of modern South Asia and the Indian Ocean, whose work critically addresses global debates on race, sovereignty, federalism, and border-making from a South Asian and anti-colonial perspective. His first book, The Boundary of Laughter: Popular Performances across Borders in South Asia (Oxford University Press, 2021), draws on archival research and ethnographic fieldwork to study Gambhira, a popular theater form performed by Hindus and Muslims in regions of the India-Bangladesh border. The book analyzes how performances of humor, laughter, and parody helped communities grapple with Partition trauma and create shared cultural spaces across colonial and post-colonial borders. It received honorable mention in the American Folklore Society’s 2022 Wayland D. Hand Prize and was longlisted for the 2022 Karwaan Prize for Indian History. Currently, De explores the broader spatial framework of the Indian Ocean, mapping connections between race, sovereignty, and federalism in British India. His research shows how racial segregation and federal structures devised by imperial administrators influenced governance, and how anticolonial federalist politics challenged racial logic, developing competing models of sovereignty that persisted after decolonization. Born and raised in Howrah, India, De was trained in South Asian and Indian Ocean History at Tufts University and Harvard University, where he earned his Ph.D. in 2024. He leads collaborative projects in vernacular languages and has contributed to edited volumes on South Asian federalist politics.

Research topics

• Computer science
• Operating system
• Embedded system
• Computer hardware
• Parallel computing

Selected publications

• A Rebel's Constitution

  2025-10-31

  book-chapter1st authorCorresponding

  Examining the Indian Constituent Assembly debates, this chapter traces a hitherto unexplored lineage of anticolonial constitutionalism in South Asia. Scholarly assessments of the Indian Constitution, by both its champions and critics, have focused almost exclusively on the text of the Constitution that was promulgated in 1950 and its paradigmatic founding fathers, Nehru and Ambedkar. In contrast, this chapter analyzes a set of lesser-known figures in the Assembly, especially H.V. Kamath and K.T. Shah, who had broken ranks with the Congress when the latter seemed keen on adopting the colonial Government of India Act (1935) as the structural basis for the Indian Republic. Drawing upon legislative proceedings and private papers, this essay shows how these “rebels” proposed an alternative anticolonial vision that resisted the incorporation of states of exception and articulated the vision for a federal India, and how this vision continued to influence political movements against authoritarianism in independent India. The trajectory of anticolonial constitutionalism, therefore, not only complicates the notion of the 1950 Constitution being the telos of the struggle for independence but also reveals the making of an alternative political vision outside the framework of the colonial state structure.

  PublisherDOI

• How Asia Found Herself: A Story of Intercultural Understanding, written by Nile Green

  Crossroads · 2025-02-17

  article1st authorCorresponding
  PublisherDOI

• Willow: a user-programmable SSD

  2014-10-06 · 112 citations

  article

  We explore the potential of making programmability a central feature of the SSD interface. Our prototype sys-tem, called Willow, allows programmers to augment and extend the semantics of an SSD with application-specific features without compromising file system protections. The SSD Apps running on Willow give applications low-latency, high-bandwidth access to the SSD’s contents while reducing the load that IO processing places on the host processor. The programming model for SSD Apps provides great flexibility, supports the concurrent execu-tion of multiple SSD Apps in Willow, and supports the execution of trusted code in Willow. We demonstrate the effectiveness and flexibility of Willow by implementing six SSD Apps and measuring their performance. We find that defining SSD semantics in software is easy and beneficial, and that Willow makes it feasible for a wide range of IO-intensive applications to benefit from a customized SSD interface. 1

  PublisherDOI

• Compute Capable Next-Generation Solid-State Drives (Ssds)

  2014-07-25

  book1st authorCorresponding
  Publisher

• A Compute Capable SSD Architecture for Next-Generation Non-volatile Memories

  2014-01-01

  reportOpen access1st authorCorresponding

  Existing storage technologies (e.g., disks and ash) are failing to cope with the processor and main memory speed and are limiting the overall perfor- mance of many large scale I/O or data-intensive applications. Emerging fast byte-addressable non-volatile memory (NVM) technologies, such as phase-change memory (PCM), spin-transfer torque memory (STTM) and memristor are very promising and are approaching DRAM-like performance with lower power con- sumption and higher density as process technology scales. These new memories are narrowing down the performance gap between the storage and the main mem- ory and are putting forward challenging problems on existing SSD architecture, I/O interface (e.g, SATA, PCIe) and software. This dissertation addresses those challenges and presents a novel SSD architecture called XSSD. XSSD o oads com- putation in storage to exploit fast NVMs and reduce the redundant data tra c across the I/O bus. XSSD o ers a exible RPC-based programming framework that developers can use for application development on SSD without dealing with the complication of the underlying architecture and communication management. We have built a prototype of XSSD on the BEE3 FPGA prototyping system. We implement various data-intensive applications and achieve speedup and energy ef- ciency of 1.5-8.9 and 1.7-10.27 respectively. This dissertation also compares XSSD with previous work on intelligent storage and intelligent memory. The existing ecosystem and these new enabling technologies make this system more viable than earlier ones.

  PublisherOA PDFDOI

• Minerva: Accelerating Data Analysis in Next-Generation SSDs

  2013-04-01 · 58 citations

  article1st authorCorresponding

  Emerging non-volatile memory (NVM) technologies have DRAM-like latency with storage-like density, offering unique capability to analyze large data sets significantly faster than flash or disk storage. However, the hybrid nature of these NVM technologies such as phase-change memory (PCM) make it difficult to use them to best advantage in the memory-storage hierarchy. These NVMs lack the fast write latency required of DRAM and are thus not suitable as DRAM equivalent on the memory bus, yet their low latency even in random access patterns is not easily exploited over an I/O bus. In this work, we describe an FPGA-based system to execute application-specific operations in the NVM controller and evaluate its performance on two microbenchmarks and a keyvalue store. Our system Minerva1extends the conventional solidstate drive (SSD) architecture to offload data or I/O intensive application code to the SSD to exploit the low latency and high internal bandwidth of NVMs. Performing computation in the FPGA-based NVM storage controller significantly reduces data traffic between the host and storage and serves as an offload engine for data analysis workloads. A runtime library enables the programmer to offload computations to the SSD without dealing with the complications of the underlying architecture and inter-controller communication management. We have implemented a prototype of Minerva on the BEE3 FPGA system. We compare the performance of Minerva to a state of the art PCIe-attached PCM-based SSD. Minerva improves performance by an order of magnitude on two microbenchmarks. Minerva based key-value store performs up to 5.2 M get operations/s and 4.0 M set operations/s which is 7.45× and 9.85× higher than the PCM-based SSD that uses the conventional I/O architecture. This huge improvement comes from the reduction of data transfer between the storage to the host and the FPGA-based data processing in the SSD.

  PublisherDOI

• Providing safe, user space access to fast, solid state disks

  ACM SIGARCH Computer Architecture News · 2012-03-03 · 17 citations

  article

  Emerging fast, non-volatile memories (e.g., phase change memories, spin-torque MRAMs, and the memristor) reduce storage access latencies by an order of magnitude compared to state-of-the-art flash-based SSDs. This improved performance means that software overheads that had little impact on the performance of flash-based systems can present serious bottlenecks in systems that incorporate these new technologies. We describe a novel storage hardware and software architecture that nearly eliminates two sources of this overhead: Entering the kernel and performing file system permission checks. The new architecture provides a private, virtualized interface for each process and moves file system protection checks into hardware. As a result, applications can access file data without operating system intervention, eliminating OS and file system costs entirely for most accesses. We describe the support the system provides for fast permission checks in hardware, our approach to notifying applications when requests complete, and the small, easily portable changes required in the file system to support the new access model. Existing applications require no modification to use the new interface. We evaluate the performance of the system using a suite of microbenchmarks and database workloads and show that the new interface improves latency and bandwidth for 4 KB writes by 60% and 7.2x, respectively, OLTP database transaction throughput by up to 2.0x, and Berkeley-DB throughput by up to 5.7x. A streamlined asynchronous file IO interface built to fully utilize the new interface enables an additional 5.5x increase in throughput with 1 thread and 2.8x increase in efficiency for 512 B transfers.

  PublisherDOI

• Providing safe, user space access to fast, solid state disks

  2012-03-03 · 158 citations

  article

  Emerging fast, non-volatile memories (e.g., phase change memories, spin-torque MRAMs, and the memristor) reduce storage access latencies by an order of magnitude compared to state-of-the-art flash-based SSDs. This improved performance means that software overheads that had little impact on the performance of flash-based systems can present serious bottlenecks in systems that incorporate these new technologies. We describe a novel storage hardware and software architecture that nearly eliminates two sources of this overhead: Entering the kernel and performing file system permission checks. The new architecture provides a private, virtualized interface for each process and moves file system protection checks into hardware. As a result, applications can access file data without operating system intervention, eliminating OS and file system costs entirely for most accesses. We describe the support the system provides for fast permission checks in hardware, our approach to notifying applications when requests complete, and the small, easily portable changes required in the file system to support the new access model. Existing applications require no modification to use the new interface. We evaluate the performance of the system using a suite of microbenchmarks and database workloads and show that the new interface improves latency and bandwidth for 4 KB writes by 60% and 7.2x, respectively, OLTP database transaction throughput by up to 2.0x, and Berkeley-DB throughput by up to 5.7x. A streamlined asynchronous file IO interface built to fully utilize the new interface enables an additional 5.5x increase in throughput with 1 thread and 2.8x increase in efficiency for 512 B transfers.

  PublisherDOI

• Providing safe, user space access to fast, solid state disks

  ACM SIGPLAN Notices · 2012-03-03 · 12 citations

  article

  Emerging fast, non-volatile memories (e.g., phase change memories, spin-torque MRAMs, and the memristor) reduce storage access latencies by an order of magnitude compared to state-of-the-art flash-based SSDs. This improved performance means that software overheads that had little impact on the performance of flash-based systems can present serious bottlenecks in systems that incorporate these new technologies. We describe a novel storage hardware and software architecture that nearly eliminates two sources of this overhead: Entering the kernel and performing file system permission checks. The new architecture provides a private, virtualized interface for each process and moves file system protection checks into hardware. As a result, applications can access file data without operating system intervention, eliminating OS and file system costs entirely for most accesses. We describe the support the system provides for fast permission checks in hardware, our approach to notifying applications when requests complete, and the small, easily portable changes required in the file system to support the new access model. Existing applications require no modification to use the new interface. We evaluate the performance of the system using a suite of microbenchmarks and database workloads and show that the new interface improves latency and bandwidth for 4 KB writes by 60% and 7.2x, respectively, OLTP database transaction throughput by up to 2.0x, and Berkeley-DB throughput by up to 5.7x. A streamlined asynchronous file IO interface built to fully utilize the new interface enables an additional 5.5x increase in throughput with 1 thread and 2.8x increase in efficiency for 512 B transfers.

  PublisherDOI

• Understanding the Impact of Emerging Non-Volatile Memories on High-Performance, IO-Intensive Computing

  2010-11-01 · 141 citations

  article

  Emerging storage technologies such as flash memories, phase-change memories, and spin-transfer torque memories are poised to close the enormous performance gap between disk-based storage and main memory. We evaluate several approaches to integrating these memories into computer systems by measuring their impact on IO-intensive, database, and memory-intensive applications. We explore several options for connecting solid-state storage to the host system and find that the memories deliver large gains in sequential and random access performance, but that different system organizations lead to different performance trade-offs. The memories provide substantial application-level gains as well, but overheads in the OS, file system, and application can limit performance. As a result, fully exploiting these memories' potential will require substantial changes to application and system software. Finally, paging to fast non-volatile memories is a viable option for some applications, providing an alternative to expensive, powerhungry DRAM for supporting scientific applications with large memory footprints.

  PublisherDOI

Frequent coauthors

• Steven Swanson

  Brigham and Women's Hospital

  7 shared

• Adrian M. Caulfield

  Microsoft (United States)

  5 shared

• Joel Coburn

  Alpha Omega Alpha Medical Honor Society

  5 shared

• Todor I. Mollov

  University of California, San Diego

  4 shared

• Louis Alex Eisner

  University of California, San Diego

  3 shared

• Rajesh K. Gupta

  University of California, San Diego

  3 shared

• Jiahua He

  Huazhong University of Science and Technology

  2 shared

• Allan Snavely

  2 shared

Awards & honors

• honorable mention in the American Folklore Society’s 2022 Wa…
• longlisted for the inaugural 2022 Karwaan Prize for the best…
• supported by major fellowships from the Social Science Resea…
• supported by the American Institute of Indian Studies
• supported by the Center for European Studies at Harvard