About

Kwabena Boahen is a Professor of Bioengineering and of Electrical Engineering at Stanford University, with a courtesy appointment in Computer Science. He is an investigator in the Bio-X Institute, the System X Alliance, and the Wu Tsai Neurosciences Institute. He founded the Brains in Silicon Lab at Stanford to link neuronal biophysics to cognitive behavior through computational modeling and to emulate the brain with silicon chips via neuromorphic engineering. His research focuses on understanding neural networks and developing hardware that mimics brain function, exemplified by projects such as Neurogrid, an iPad-sized platform that emulates the cerebral cortex in biophysical detail and at functional scale, which previously required a supercomputer. Boahen earned his doctorate in Computation and Neural Systems at Caltech in 1997, after completing his undergraduate studies in Electrical and Computer Engineering at Johns Hopkins University in 1985. He has held faculty positions at the University of Pennsylvania and has received numerous honors, including a Packard Fellowship, a NIH Director’s Pioneer Award, and fellowships in the American Institute for Medical and Biological Engineering and the IEEE. His work has resulted in over a hundred publications, including features in Scientific American, and he has been a prominent speaker at conferences and events, including a TED talk titled 'A computer that works like the brain'.

Research topics

• Computer Science
• Artificial Intelligence
• Data science
• Mathematics
• Physics
• Psychology
• Engineering
• Cognitive science
• Biology
• Mechanical engineering
• Programming language
• Geometry

Selected publications

• Axonal ensembles repeatedly cluster and order synapses along dendrites in mouse cortex

  bioRxiv (Cold Spring Harbor Laboratory) · 2026-04-03

  articleOpen accessSenior author

  Abstract Neuronal ensembles—groups of neurons that exhibit coordinated activity during behavior—are a fundamental feature of cortical computation. Dendritic branches amplify clustered synaptic inputs through local nonlinearities, suggesting that presynaptic groups might organize their connections in specific spatial patterns to engage these mechanisms. Whether the same axon groups form synaptic clusters with consistent spatial arrangements across different target neurons remains unknown, but nanoscale connectomes would resolve such anatomical motifs if they exist. We analyzed millions of synaptic connections in a connectome of mouse visual cortex and found over 700,000 axon groups that repeatedly cluster their synapses onto dendritic branches of multiple pyramidal cells, with over 500,000 maintaining consistent distal-to-proximal arrangements. These repeated patterns occur far more frequently than expected from spatial proximity or layer-based connectivity rules. Axon groups preferentially target specific dendritic branches and position their synapses in stereotyped spatial configurations across multiple postsynaptic partners, revealing that functional ensembles leave characteristic anatomical signatures in cortical microarchitecture.

  PublisherDOI

• ColBERT-Serve: Efficient Multi-stage Memory-Mapped Scoring

  Lecture notes in computer science · 2025-01-01 · 2 citations

  book-chapter
  PublisherDOI

• Hierarchical Event Readout with Asynchronous Pipelined Opportunistic Merges

  2025-05-11

  articleSenior author

  Event cameras asynchronously output a stream of words that encode the location, time, and sign of a luminance change that a pixel detects. When these events are sparse, one is read out of a 1024-by-1024-pixel with a 352ns latency, the time it takes to cycle from one row to another. But when more than one event occurs per cycle, this readout latency balloons to 180μs, the time it takes to cycle through half of the rows. Here we shorten this queue by reading out single events faster. Instead of selecting and addressing rows and columns, we select and address squares of exponentially increasing size. A 5-level–16-ary tree merges these squares’ events hierarchically in a predetermined order. Asynchronous pipeline stages break up long datapaths to output a 16-bit word every 5ns, read an event out with a 51ns latency, and stream out events from all 1M pixels in 350μs (3.0Geps). By reading a single event out 7 times faster than row–column, hierarchical shortens the queue 500-fold and cuts latency 3,500-fold.

  PublisherDOI

• A Low Thermal Sensitivity Subthreshold-Current to Pulse-Frequency Converter for Neuromorphic Chips

  IEEE Journal on Emerging and Selected Topics in Circuits and Systems · 2023-10-02 · 1 citations

  articleSenior author

  To convert a subthreshold current to a pulse frequency efficiently and predictably, we designed a silicon soma that conserves energy with current feedback and lessens thermal sensitivity with voltage feedback. When the input current charges a capacitor close to the inversion point of an inverter, its short-circuit current wastes energy. To shorten this period, existing designs accelerate the charging rate with positive feedback: Either a capacitive divider feeds back voltage or a current mirror feeds back current. Voltage feedback is less effective because it kicks in only at the inversion point. Current feedback is less predictable because its leakage current is exponentially sensitive to temperature variation. By quantifying this thermal sensitivity with an analytic model of the subthreshold MOS transistor, we successfully combined current feedback with voltage feedback to design a silicon soma 10-fold less sensitive to temperature than a previous current-feedback-only design that uses 7.6-fold more silicon area. This advance allowed a mixed-signal neuromorphic chip to be predictably programmed for the first time.

  PublisherDOI

• Energy-efficient detection of a spike sequence

  2023-01-01

  articleOpen accessSenior author

  We present a novel 3D spike sorting network (3DSS) that detects a spike sequence efficiently and memorizes it upon a single presentation without configuration.We analyze the wiring and switches of alternatives and show that 3DSS reduces energy per spike quadratically compared to existing 2D networks.Applications include large-scale document retrieval and self-configuring hardware.

  PublisherOA PDFDOI

• An Analytical MOS Device Model With Mismatch and Temperature Variation for Subthreshold Circuits

  IEEE Transactions on Circuits & Systems II Express Briefs · 2023-01-03 · 9 citations

  articleSenior author

  Subthreshold analog circuits are attractive for low-power, large-scale neuromorphic systems. However, subthreshold currents are exponentially sensitive to temperature and device mismatch, and a compact model that accounts for these effects is needed. We develop an analytical compact model with mismatch and temperature variation for subthreshold MOS devices. The model only requires an initial set of Monte Carlo (MC) simulations on individual devices for parameter extraction. Then the designer can use its parameterized analytical expressions for circuit design, instead of running repeated MC simulations on large circuits. We apply this model to a subthreshold current mirror design example. Good agreement between the developed model and Spectre simulations is achieved in a 28-nm fully-depleted silicon-on-insulator (FDSOI) process. The model is general and can also guide the design of other subthreshold circuits, such as low-power silicon neurons. It has been used to design Braindrop, the first neuromorphic chip programmed at a high level of abstraction.

  PublisherDOI

• Multi-gate FeFET Discriminates Spatiotemporal Pulse Sequences for Dendrocentric Learning

  2023-12-09

  articleSenior author

  This paper presents a dendrite-like device that discriminates spatiotemporal patterns of pulses for parallel processing in 3D neuromorphic architectures. The device utilizes the ferroelectric layer in a segmented multi-gate FeFET design to detect a consecutive sequence of input pulses. Experimental results demonstrate successful emulation of highly selective sequence discrimination in dendrites of neurons in the cortex and highlight up to 100× signal-margin (output current differences). This nanodendrite design offers a neuromorphic solution to thermally scalable parallel processing in 3D systems.

  PublisherDOI

• Catalyzing next-generation Artificial Intelligence through NeuroAI

  Nature Communications · 2023 · 276 citations

  • Computer Science
  • Artificial Intelligence
  • Computer Science

  Neuroscience has long been an essential driver of progress in artificial intelligence (AI). We propose that to accelerate progress in AI, we must invest in fundamental research in NeuroAI. A core component of this is the embodied Turing test, which challenges AI animal models to interact with the sensorimotor world at skill levels akin to their living counterparts. The embodied Turing test shifts the focus from those capabilities like game playing and language that are especially well-developed or uniquely human to those capabilities - inherited from over 500 million years of evolution - that are shared with all animals. Building models that can pass the embodied Turing test will provide a roadmap for the next generation of AI.

  PublisherOA PDFDOI

• Toward Next-Generation Artificial Intelligence: Catalyzing the NeuroAI Revolution

  arXiv (Cornell University) · 2022 · 33 citations

  • Computer Science
  • Artificial Intelligence
  • Cognitive science

  Neuroscience has long been an essential driver of progress in artificial intelligence (AI). We propose that to accelerate progress in AI, we must invest in fundamental research in NeuroAI. A core component of this is the embodied Turing test, which challenges AI animal models to interact with the sensorimotor world at skill levels akin to their living counterparts. The embodied Turing test shifts the focus from those capabilities like game playing and language that are especially well-developed or uniquely human to those capabilities, inherited from over 500 million years of evolution, that are shared with all animals. Building models that can pass the embodied Turing test will provide a roadmap for the next generation of AI.

  PublisherOA PDFDOI

• Optimal noise level for coding with tightly balanced networks of spiking neurons in the presence of transmission delays

  PLoS Computational Biology · 2022-10-17 · 30 citations

  articleOpen access

  Neural circuits consist of many noisy, slow components, with individual neurons subject to ion channel noise, axonal propagation delays, and unreliable and slow synaptic transmission. This raises a fundamental question: how can reliable computation emerge from such unreliable components? A classic strategy is to simply average over a population of N weakly-coupled neurons to achieve errors that scale as [Formula: see text]. But more interestingly, recent work has introduced networks of leaky integrate-and-fire (LIF) neurons that achieve coding errors that scale superclassically as 1/N by combining the principles of predictive coding and fast and tight inhibitory-excitatory balance. However, spike transmission delays preclude such fast inhibition, and computational studies have observed that such delays can cause pathological synchronization that in turn destroys superclassical coding performance. Intriguingly, it has also been observed in simulations that noise can actually improve coding performance, and that there exists some optimal level of noise that minimizes coding error. However, we lack a quantitative theory that describes this fascinating interplay between delays, noise and neural coding performance in spiking networks. In this work, we elucidate the mechanisms underpinning this beneficial role of noise by deriving analytical expressions for coding error as a function of spike propagation delay and noise levels in predictive coding tight-balance networks of LIF neurons. Furthermore, we compute the minimal coding error and the associated optimal noise level, finding that they grow as power-laws with the delay. Our analysis reveals quantitatively how optimal levels of noise can rescue neural coding performance in spiking neural networks with delays by preventing the build up of pathological synchrony without overwhelming the overall spiking dynamics. This analysis can serve as a foundation for the further study of precise computation in the presence of noise and delays in efficient spiking neural circuits.

  PublisherOA PDFDOI

Recent grants

• NIH Grant DP1OD000965

  NIH · $3.9M · 2011

• CAREER: Neuromorphic Computation in Silico

  NSF · $375k · 2001–2007

• Collaborative Research: Seer: A Gigascale Neuromorphic Visual System

  NSF · $273k · 2006–2009

• NIH Grant R01NS076460

  NIH · $4.4M · 2017

Frequent coauthors

• John V. Arthur

  26 shared

• Bertram E. Shi

  Hong Kong University of Science and Technology

  19 shared

• Paul Merolla

  16 shared

• Ben Varkey Benjamin

  Stanford University

  13 shared

• Andreas G. Andreou

  13 shared

• Kareem A. Zaghloul

  National Institute of Neurological Disorders and Stroke

  9 shared

• T.Y.W. Choi

  Hong Kong University of Science and Technology

  8 shared

• Ashok Cutkosky

  7 shared

Labs

• Brains in SiliconPI

  These are current and past lab members

Education

• Ph.D., Bioengineering

  Stanford University

  1997

• M.S., Bioengineering

  Stanford University

  1993

• B.S., Physics

  California Institute of Technology

  1990

Awards & honors

• Packard Fellowship for Science and Engineering (1999)
• National Institutes of Health Director’s Pioneer Award (2006…
• Fellow of the American Institute for Medical and Biological…
• Fellow of the Institute of Electrical and Electronic Enginee…