About

Professor Ben Calhoun leads the Robust Low Power VLSI Group at the University of Virginia School of Engineering and Applied Science. His research focuses on modern VLSI design challenges, particularly power and variation issues in deep sub-micron technologies. The group investigates low power digital circuit design, sub-threshold digital circuits, SRAM design for end-of-the-roadmap silicon, variation-tolerant circuit design methodologies, and medical applications for low energy electronics. Professor Calhoun's work includes innovations in silicon-level electronics for computing, communication, and power management, enabling ultra-compact and unobtrusive wearable technologies. His research aims to develop battery-free, ultra-low-power electronics that can improve healthcare access, facilitate sustainable sensing networks, and advance wearable tech. He is recognized for his design innovations in ultra-low-power circuits and has contributed to creating sustainable hardware for sensor networks, supporting the future development of large-scale Internet-of-Things (IoT) applications.

Research topics

• Computer Science
• Electrical engineering
• Engineering
• Mathematics
• Algorithm
• Electronic engineering
• Arithmetic
• Combinatorics
• Theoretical computer science
• Operating system
• Physics
• Embedded system
• Computational science
• Computer architecture

Selected publications

• A Sub-μW Digital Temperature Compensation Architecture for Arbitrary Voltage and Current Reference Generation

  2025-05-25

  articleSenior author

  Traditionally, both reference circuits and the components they supply are designed independently to be as immune to temperature change as practical, but this requires power and area overhead to achieve. These overheads can compound in complex systems or consume excessive portions of a low power budget. In contrast, we propose a sub-μwatt digital temperature compensation architecture that generates voltage and current references with a user-defined temperature response rather than a fixed, near-ideal response. This flexible approach allows a single programmable design to be reused easily to produce different profiles over temperature, reducing design time. It also can reduce the temperature non-linearity in the components it supports by providing an input temperature profile that effectively cancels that non-linear response to allow components to operate at their target spec and eliminate excess power consumption. This approach allows designers to prioritize power consumption in their designs and use this compensation strategy to manage performance across temperature.

  PublisherDOI

• Guest Editorial Introduction to the Special Section on the 2024 IEEE International Solid-State Circuits Conference (ISSCC)

  IEEE Journal of Solid-State Circuits · 2025-01-01

  editorial
  PublisherDOI

• Modeling and Prototyping of IoT-based Long Range Self-powered Image Sensing System

  2025-05-06

  articleOpen accessSenior author

  This work introduces a long-range self-powered image sensing system for smart civil infrastructure, which addresses the challenges of high energy consumption and the need for frequent battery replacements. Existing camera solutions for long-range image transmission are energy intensive, while conventional self-powered systems operate in different contexts and do not fully meet the requirements of long-range image transmission. This paper examines how to enable battery-less cameras by presenting a model that quantifies energy consumption based on factors such as image resolution, transmission distance, and network selection. Using this model, a prototype design is optimized for energy-efficient long-range image transmission. The prototype achieves an energy consumption of 0.13 mJ per pixel per image transmission, making it 2.3x more efficient than current state-of-the-art solutions. By bridging theoretical modeling with practical deployment, this work enables scalable, real-time visual data collection for smart infrastructure monitoring in remote or hard-to-reach locations.

  PublisherOA PDFDOI

• TexCAC: A 22nm 4.8mm$^2$ 18pJ/Cycle Direct-Textile-Attachable Microcontroller Integrating 2MB MRAM for the Command and Control of Advanced Smart Textiles

  2025-09-08

  article

  We present TexCAC, the world's first direct-textileattachable, NVM-based MCU for the command and control of advanced smart textiles. Fabricated in 22 nm, it occupies merely <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4.8 ~\text{mm}^{2}$</tex> while integrating 2 MB MRAM-offering a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4 \times \sim \mathbf{1 1 4} \times$</tex> increase in NVM capacity over state-of-the-art designs of comparable or larger area. Measured fully on-textile, TexCAC achieves an optimal active energy of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$18 \text{pJ}$</tex> cycle at 0.52 V, rivaling the efficiency of leading MCU implementations.

  PublisherDOI

• Characterization of Stacked PV Cell Configurations in a Deep N-Well 65nm CMOS Technology

  2025-05-25 · 1 citations

  articleSenior author

  The selection of a suitable photovoltaic (PV) design for emerging energy harvesting applications remains challenging, as PV cell performance is highly dependent on design variables and environmental setup. These factors vary widely across existing studies, making direct comparisons complex and increasing uncertainty in predicting expected PV cell output characteristics for a given use case. To address this, our paper presents a comparison of various on-chip PV cell configurations, implemented using a 0.6mm x 0.6mm test chip realized in 65nm deep-nwell (DNW) CMOS technology. The experimental results demonstrate that, depending on diode arrangements, separate configurations achieve a maximum open-circuit voltage of 0.54V and a peak power density of 1.18 µW/mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at 20 klux illumination. This characterization work, therefore, enables designers to select an optimal configuration tailored to specific application scenarios.

  PublisherDOI

• A Cooperative 0.6×1.2mm Fully on-Chip Switched-Capacitor Voltage Regulator with Communication-Free Multi-Chip Output Voltage Matching for Distributed Power Management in Networks-on-Textiles

  2025-09-08

  articleSenior author

  A cooperative fully on-chip switched-capacitor voltage regulator (SCVR) in 65 nm CMOS implements a communication-free distributed power delivery system for Networks-on-Textiles (kNOTs). The design enables multiple chips to act in parallel to scale output current and improve load regulation. Utilizing a proposed voltage matching technique to mitigate charge redistribution and current imbalances, the system achieves a peak efficiency exceeding 72.5 % from one to six SCVRs in parallel. The output current at peak efficiency increased by <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$8.6 \times$</tex> with six SCVRs compared with just one SCVR. The proposed circuits have also been integrated on a textile swatch and demonstrated cooperatively powering an in-textile system to deliver 1.8 V from a 3.0 V input supply.

  PublisherDOI

• A Fully Integrated, Custom End-to-End PPG Sensing System for Ultra-Low Power Wearables

  2025-05-25

  articleSenior author

  Photoplethysmography (PPG) is a widely adopted technique for monitoring essential physiological parameters like heart rate and blood oxygen saturation (SpO2). The increasing demand for wearable health monitoring devices necessitates the development of energy-efficient PPG systems. This paper proposes an ultra-low power, end-to-end PPG sensing system with continuous monitoring capabilities. The system consists of three distinct chips: a system-on-chip, an analog-front end chip, and a Bluetooth low-energy transmitter, enabling real-time PPG data transmission to a smartphone. All components are fabricated using the bulk 65 nm low-power CMOS process. This system achieves minimal power consumption of 18.78 µW during idle periods and 148.5 µW during active data transmission when aggressively duty-cycled at 2.4%.

  PublisherDOI

• A 0.36 mm² On-the-Fly I2C-to-SPI Converter for E-Textile Applications

  2025-05-25

  articleSenior author

  This paper presents a 0.36-mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> I2C-to-SPI converter chip with on-the-fly conversion for E-textile applications. The on-the-fly operation eliminates the need for on-chip data buffers and clock generation, improving the area and power efficiency versus prior works. The die area is 7.33× smaller than commercially-available off-the-shelf (COTS) I2Cto-SPI converters, enabling it to integrate unobtrusively into E-textile applications. The chip supports conversion at ultra-fast I2C operating frequency up to 5 MHz while consuming only 0.379 mW of power. At the standard I2C speed of 400 kHz, it consumes 0.145 mW, which is 48× more power-efficient than commercially available I2C-to-SPI converters.

  PublisherDOI

• 37.2 A 2-Dimensional mm-Scale Network-on-Textiles (kNOTs) for Wearable Computing with Direct Die-to-Yarn Integration of 0.6×2.15mm² SoC and bySPI Chiplets

  2025-02-16 · 4 citations

  articleSenior author

  This paper proposes a scalable, 2-dimensional network-on-textiles (kNOT) comprised of systems-on-chip (SoCs) and “bySPI” networking chiplets that are jointly capable of supporting heterogeneous programming, multiple sensing modalities, and a distributed memory system. Emerging e-textiles must retain the flexibility and comfort of their host garment to be viable in wearable applications for healthcare, virtual reality, and sports [1]–[4]. Prior integration efforts have demonstrated textile computing by weaving flexible filament circuits [5]–[7], embroidering conductive yarns [8], and fabricating electronic fibers [9]–[10]. Still, these works suffer from a combination of bulky, rigid components, high cost, or 1-dimensionality (Fig. 37.2.1). To preserve the textile's look and feel, SoCs for fabric integration must also be highly miniaturized, feature minimal area-hungry IO interfaces, be easily programmable, and be fully integrable. The e-textile system in [11] integrated a health sensing chip onto a planar fashionable circuit board, yet the board (25×25mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>) is 40× larger than the chip itself. The System-in-Fiber from [12] is fully autonomous but has many IO pads, is limited to 1D networks, and requires an interposer (4.7×3.7mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>) that is 3.8× larger than the die. Most recently, a battery-less e-textile system in [13] integrates cm-scale harvesting tiles and an inductor onto a shirt, but it lacks an integrated SoC. Many wearable applications also demand substantial on-garment storage, yet large memories are unsuited for comfortable textile integration due to their sizable footprint. Our kNOT solution addresses this by replacing monolithic memory units with a distributed set of smaller memories. However, networking these chiplets via existing bus standards incurs significant area and power penalties [14]. Existing Body Area Networks highlight the potential of multi-chip solutions, but they lack seamless textile integration [15]–[17]. Hence, to truly realize a fabric computing system, we propose a board and interposer-free 2D kNOT built with the direct-die attachment of two miniaturized chiplets: 1) an SoC with an array of reconfigurable pads, fault-tolerant global bootup, SoC-to-SoC clock synchronization, and dynamic network configuration; and 2) a bySPI chiplet which is a COTS-compatible, reduced-wire enhancement of the bypass-SPI (bySPI) protocol [14] capable of connecting to any number of receivers (RXs) using three wires. The chiplets are directly interconnected to braided composite yarns, which are comprised of para-aramid structural yarns and insulated 25μm-diameter conductors [26]. For each pad, a yarn is embroidered into a cotton substrate and its insulation is selectively ablated using a laser. Solder paste is deposited, the chiplet is placed to align its pads with the yarns, and the solder is reflowed. The interconnections are then encapsulated to provide mechanical and environmental protection. This textile-chiplet interconnection approach is compatible with automated high-throughput 2.5D electronics manufacturing methods, enabling the production of textile-integrated systems at scale (Fig. 37.2.1).

  PublisherDOI

• kNOT: A 2-D Distributed Network-on-Textile Architecture With Direct Die-to-Yarn Integration of 0.6 × 2.15 mm ² SoC and bySPI Chiplets for Wearable Computing

  IEEE Journal of Solid-State Circuits · 2025-11-04

  articleSenior author

  This article presents kNOT, a scalable, distributed, and 2-D Network-On-Textile (kNOT) comprising miniaturized systems on chip (SoCs) and bypass SPI (bySPI) networking chiplets that together enable diverse networking and computational tasks. To preserve garment comfort and flexibility, kNOT eliminates bulky boards and interposers through direct-die attachment to embroidered yarns. The SoC features reconfigurable IO pads, global fault-tolerant bootup, and high-precision clock synchronization, while the bySPI chiplet implements a compact, COTS-compatible three-wire SPI protocol supporting group access, soft-reset, and direction-controlled routing. Together, they support distributed programming, synchronized timestamping, and efficient inter-chiplet communication. The chiplets, fabricated in 65-nm CMOS, demonstrate robust operation across a textile network interfacing with commercial sensors and memories. Operating at 1.8 V with on-chip 1.12-V regulation, the SoC consumes power of 1.98 mW at 50 MHz, and bySPI consumes 0.22 mW at 25 MHz. This high integrability and functionality position kNOT as a promising foundation for scalable, garment-spanning wearable intelligence.

  PublisherDOI

Recent grants

• SHF: Small: Energy Efficient Reconfigurable Logic for Ultra Low Power Ubiquitous Computing Systems

  NSF · $400k · 2011–2015

• E2CDA: Type I: Collaborative Research: A Fast 70mV Transistor Technology for Ultra-Low-Energy Computing

  NSF · $435k · 2016–2020

• CPS: Synergy: Collaborative Research: Towards Dependable Self-Powered Things for the IoT

  NSF · $533k · 2016–2020

• SHF: Small: Variation "Immune System" for Ultra Low Power Systems-on-Chip

  NSF · $425k · 2014–2018

• CSR: Small: Collaborative Research: A Wireless Batteryless System-on-a-Chip Platform for the Internet of Things

  NSF · $270k · 2014–2017

Frequent coauthors

• James Boley

  62 shared

• Panagiotis Sismanoglou

  University of Patras

  49 shared

• Emre Salman

  Stony Brook University

  49 shared

• Wen‐Tsung Huang

  Chi Mei Medical Center

  49 shared

• Fadi Kurdahi

  University of California, Irvine

  49 shared

• Hailang Wang

  Southwest Forestry University

  49 shared

• Youngmin Kim

  Korea Advanced Institute of Science and Technology

  49 shared

• David W. Graham

  West Virginia University

  49 shared

Education

• B.S., Electrical Engineering with a concentration in Computer Science

  University of Virginia

  2000

Awards & honors

• Fellow of IEEE