About

Daniel J. Sorin is a professor specializing in computer architecture with a research focus on automatic generation of coherence protocols, solving architecture problems with coding theory, automated development of accelerators, fault-tolerant computer architecture, and verification-aware computer architecture. He teaches advanced courses such as ECE 652/CS 650: Advanced Computer Architecture II. His work involves developing innovative solutions to complex architectural challenges, leveraging coding theory to enhance system reliability and performance. Professor Sorin also mentors a range of graduate and undergraduate students, guiding research in cutting-edge areas of computer architecture.

Research topics

• Computer Science
• Computer architecture
• Parallel computing
• Artificial Intelligence
• Embedded system
• Computer engineering
• Engineering
• Operating system
• Computer hardware

Selected publications

• Efficient Deadlock Avoidance by Considering Stalling, Message Dependencies, and Topology

  IEEE Computer Architecture Letters · 2025-07-01

  articleSenior author

  Traditional schemes for avoiding deadlocks compose techniques for both protocol deadlocks (virtual networks) and network deadlocks (virtual channels). Recent work has shown how to use fewer virtual networks by analyzing protocol stalls instead of just considering the longest chain of causally dependent messages. We identify a shortcoming in this work, which can lead to deadlocks, and show that combining stall analysis with analyses of message dependencies and topology can avoid deadlocks while using fewer buffers than the conventional approach.

  PublisherDOI

• Rigorous Evaluation of Microarchitectural Side-Channels with Statistical Model Checking

  ArXiv.org · 2025-10-02

  preprintOpen accessSenior author

  Rigorous quantitative evaluation of microarchitectural side channels is challenging for two reasons. First, the processors, attacks, and defenses often exhibit probabilistic behaviors. These probabilistic behaviors arise due to natural noise in systems (e.g., from co-running processes), probabilistic side channel attacks, and probabilistic obfuscation defenses. Second, microprocessors are extremely complex. Previous evaluation methods have relied on abstract or simplified models, which are necessarily less detailed than real systems or cycle-by-cycle simulators, and these models may miss important phenomena. Whereas a simple model may suffice for estimating performance, security issues frequently manifest in the details. We address this challenge by introducing Statistical Model Checking (SMC) to the quantitative evaluation of microarchitectural side channels. SMC is a rigorous statistical technique that can process the results of probabilistic experiments and provide statistical guarantees, and it has been used in computing applications that depend heavily on statistical guarantees (e.g., medical implants, vehicular computing). With SMC, we can treat processors as opaque boxes, and we do not have to abstract or simplify them. We demonstrate the effectiveness of SMC through three case studies, in which we experimentally show that SMC can evaluate existing security vulnerabilities and defenses and provide qualitatively similar conclusions with greater statistical rigor, while making no simplifying assumptions or abstractions. We also show that SMC can enable a defender to quantify the amount of noise necessary to have a desired level of confidence that she has reduced an attacker's probability of success to less than a desired threshold, thus providing the defender with an actionable plan for obfuscation via noise injection.

  PublisherOA PDFDOI

• Determining the Minimum Number of Virtual Networks for Different Coherence Protocols

  2024-06-29 · 5 citations

  articleOpen accessSenior author

  We revisit the question of how many virtual networks (VNs) are required to provably avoid deadlock in a cache coherence protocol. The textbook way of reasoning about VNs says that the number of VNs depends on the longest chain of message dependencies in the protocol. We show that this conventional wisdom is incorrect and results in a number of virtual networks that is neither necessary nor sufficient for the general system model of an arbitrary interconnection network (ICN) topology and multiple directories. We have created a formalism for modeling coherence protocols and their interactions with ICN queueing. Using that formalism, we have developed an algorithm that (a) determines the minimum number of virtual networks required to avoid deadlock and (b) generates the mappings from message types to virtual networks.

  PublisherOA PDFDOI

• PipeGen: Automated Transformation of a Single-Core Pipeline into a Multicore Pipeline for a Given Memory Consistency Model

  2024-10-11

  articleOpen access

  Designing a pipeline for a multicore processor is difficult. One major challenge is designing it such that the pipeline correctly enforces the intended memory consistency model (MCM). We have developed the PipeGen design automation tool to allow architects to start with a single core pipeline that only enforces single-threaded correctness and automatically transform it to enforce a given MCM. Our key innovation is a set of compiler-like transformations that codify three different ways of enforcing memory ordering at the pipeline. We have validated that PipeGen correctly enforces the ARMv8 and x86TSO MCMs on three distinct pipeline implementations, using litmus tests with the Murphi model checker.

  PublisherDOI

• Low-Energy Line Codes for On-Chip Networks

  arXiv (Cornell University) · 2024-05-23

  preprintOpen accessSenior author

  Energy is a primary constraint in processor design, and much of that energy is consumed in on-chip communication. Communication can be intra-core (e.g., from a register file to an ALU) or inter-core (e.g., over the on-chip network). In this paper, we use the on-chip network (OCN) as a case study for saving on-chip communication energy. We have identified a new way to reduce the OCN's link energy consumption by using line coding, a longstanding technique in information theory. Our line codes, called Low-Energy Line Codes (LELCs), reduce energy by reducing the frequency of voltage transitions of the links, and they achieve a range of energy/performance trade-offs.

  PublisherOA PDFDOI

• Rigorous Evaluation of Computer Processors with Statistical Model Checking

  Zenodo (CERN European Organization for Nuclear Research) · 2023-10-28

  paratextOpen accessSenior author

  Artifact for MICRO'23

  PublisherDOI

• HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols

  IEEE Micro · 2023-05-11 · 1 citations

  article

  We address the two challenges architects face when designing heterogeneous processors with cache-coherent shared memory. First, we introduce HeteroGen, an automated tool for composing clusters of cores, each with its own coherence protocol. Second, we show that the output of HeteroGen conforms to a precisely defined memory consistency model that we call a compound consistency model. We also demonstrate that HeteroGen can correctly fuse a wide range of coherence protocols. Our experiments indicate that protocols generated by HeteroGen perform comparably to a publicly available manually generated heterogeneous protocol.

  PublisherDOI

• Session details: Session 2B: Microarchitecture

  2023-10-28

  article1st authorCorresponding

  No abstract available.

  PublisherDOI

• Rigorous Evaluation of Computer Processors with Statistical Model Checking

  2023-10-28 · 6 citations

  articleOpen accessSenior author

  Experiments with computer processors must account for the inherent variability in executions. Prior work has shown that real systems exhibit variability, and random effects must be injected into simulators to account for it. Thus, we can run multiple executions of a given benchmark and generate a distribution of results. Prior work uses standard statistical techniques that are not suitable. While the result distributions may take any forms that are unknown a priori, many works naively assume they are Gaussian, which can be far from the truth. To allow rigorous evaluation for arbitrary result distributions, we introduce statistical model checking (SMC) to the world of computer architecture. SMC is a statistical technique that is used in research communities that depend heavily on statistical guarantees. SMC provides a rigorous mathematical methodology that employs experimental sampling for probabilistic evaluation of properties of interest, such that one can determine with a desired confidence whether a property (e.g., System X is 1.1x faster than System Y) is true or not. SMC alone is not enough for computer architects to draw conclusions based on their data. We create an end-to-end framework called SMC for Processor Analysis (SPA) which utilizes SMC techniques to provide insightful conclusions given experimental data.

  PublisherOA PDFDOI

• HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols

  2022-04-01 · 14 citations

  articleOpen access

  We solve the two challenges architects face when designing heterogeneous processors with cache coherent shared memory. First, we develop an automated tool, called HeteroGen, for composing clusters of cores, each with its own coherence protocol. Second, we show that the output of HeteroGen adheres to a precisely defined memory consistency model that we call a compound consistency model. For a wide variety of protocols—including the MOESI variants, as well as those that are targeted towards Total Store Order and Release Consistency—we show that HeteroGen can correctly fuse them. To validate HeteroGen, we develop the first litmus tests for verifying that heterogeneous protocols satisfy compound consistency models. To understand the possible performance implications of automatic protocol generation, we compared against a publicly available manually-generated heterogeneous protocol. Our results show that performance is comparable.

  PublisherOA PDFDOI

Recent grants

• SHF: Small: Commodity Processors with Mainframe Reliability

  NSF · $420k · 2011–2015

• SHF: Small: Automatic Generation of Cache Coherent Memory Systems for Multicore Processors

  NSF · $400k · 2020–2024

• SHF: Small: Shared Memory Architectures and Microarchitectures for Heterogeneous General-Purpose Chips

  NSF · $300k · 2012–2016

• CPA-CSA: Verification-Aware Microarchitecture

  NSF · $220k · 2008–2012

• SHF: Small: Using Coding Theory to Optimize the Representation of Information in Computer Architecture

  NSF · $458k · 2014–2018

Frequent coauthors

• Mark D. Hill

  Microsoft (United States)

  50 shared

• David A. Wood

  Brigham Young University

  41 shared

• Milo M. K. Martin

  Google (United States)

  21 shared

• Albert Meixner

  21 shared

• Vijay Nagarajan

  University of Utah

  18 shared

• Alvin R. Lebeck

  Duke University

  17 shared

• Sule Ozev

  Arizona State University

  16 shared

• Manoj Plakal

  University of Wisconsin–Madison

  12 shared

Labs

• Daniel Sorin LabPI

Awards & honors

• Program Chair of HiPEAC 2017
• Co-chair of selection committee for IEEE Micro's Top Picks 2…
• IEEE Micro Top Pick (2016)
• Associate Editor in Chief, Computer Architecture Letters (20…
• Best Paper Award, 20th International Symposium on High Perfo…