About

Elaheh (Eli) Bozorgzadeh is a professor in the Department of Computer Science at UC Irvine's Donald Bren School of Information & Computer Sciences. Her research interests include design automation and synthesis for reconfigurable and embedded systems, architectural synthesis and design of hybrid reconfigurable computing systems, and VLSI CAD for FPGAs and ASICs. She earned her Ph.D. from UCLA in 2003. Dr. Bozorgzadeh's work focuses on various aspects of computer system definition, design, and optimization, contributing to the advancement of computing technologies in these areas.

Research topics

• Computer Science
• Embedded system
• Computer architecture
• Computer Security
• Artificial Intelligence
• Distributed computing
• Computer network
• Operating system

Selected publications

• Exploiting and Extracting Workload Patterns for Efficient IoT Processing

  2025-06-10 · 1 citations

  articleSenior author

  Edge computing has become crucial for managing compute-intensive tasks in Internet of Things (IoT) and Cyber-Physical Systems (CPS) where resource-constrained devices seek offloading tasks to nearby edge servers. Conventional scheduling approaches, such as first-come-first-served (FCFS), frequently incur significant dynamic Processing Element (PE) transition overhead, substantially increasing the system latency. However, when multiple end devices transmit acceleration requests at constant rates, temporal patterns emerge in task arrival sequences. This paper proposes a sequence-based and an optimized cluster-based pattern extraction framework to exploit regularities in the entire workload for efficient resource allocation in multi-accelerator edge server systems processing heterogeneous tasks. Whereas the sequence-based approach utilizes a statistical method, the cluster-based approach employs a machine-learning-enabled hierarchical clustering algorithm to derive representative task patterns to generate a static scheduling guideline, exploiting task similarity in occurrence and arrival time. The lightweight scheduler dynamically allocates optimal PEs based on the guideline to maximize acceleration performance. Experiment results show that the proposed cluster-based method achieves up to 4.1x shorter wait time and 2.5x faster response times on average compared to the sequence-based approach, while maintaining near-zero drop rates in dynamic, high-load scenarios.

  PublisherDOI

• Survey of FPGA-Based Accelerators for Large Language Models

  SSRN Electronic Journal · 2025-01-01

  preprintOpen accessSenior author
  PublisherDOI

• Dynamic Multi-Accelerator Management for Deep Learning Applications on the FPGA Edge

  2025-09-10

  articleSenior author

  The emerging FPGA-based edge computing systems enable IoT devices to offload compute-intensive tasks to the edge for custom hardware acceleration. The FPGA edge provides a shared multi-accelerator platform where various hardware accelerators are dynamically allocated and accessed by multiple applications. We propose ReinConfig, a deep-reinforcement-learning-based runtime system software for an FPGA-based multi-accelerator edge platform. ReinConfig supports concurrent scheduling and asynchronous learning, capturing the characteristics of incoming task loads and adaptively learning through interactions with the system to dynamically provide efficient task scheduling and accelerator allocation. We deployed ReinConfig for deep-learning-based vision applications such as object detection and classification. Experimental results show that ReinConfig outperforms the first-come, first-served approach with $1.4 \times$ higher throughput and $20.1 \%$ lower task drop rate. It also surpasses related learning-based approaches with $1.3 \times$ higher throughput, $16.3 \%$ lower task drop rate, and $2 \times$ shorter response time on average.

  PublisherDOI

• Optimizing Lightweight Cryptographic Algorithms for Enhanced Performance and Security in IoT Medical Devices

  2024

  Senior authorCorresponding
  • Computer Science
  • Computer Science
  • Computer Security

  My research optimizes three lightweight cryptographic algorithms—AES-256, ChaCha20, and Speck—for enhanced performance and security in IoT medical devices. By analyzing these algorithms throughput, latency, and memory usage on an Arduino board and applying specific optimization techniques, I have improved these algorithms and extrapolated the results to diagnostic, monitoring, and wearable devices. The core focus is finding the optimal tradeoff between security and performance for each optimized algorithm. The less memory usage the algorithm takes up in the device, the greater the performance. However, this also leads to lesser security. Finding the optimal balance will reduce computational overhead, improve processing speed, and lower energy consumption, leading to faster data processing. I strongly believe that these improvements to the algorithms will significantly enhance the functionality, security, and reliability of IoT medical devices, improving patient outcomes and advancing healthcare technology as a whole.

  PublisherOA PDFDOI

• On Exploiting Patterns For Robust FPGA-based Multi-accelerator Edge Computing Systems

  Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 · 2022 · 5 citations

  Senior authorCorresponding
  • Computer Science
  • Computer Science
  • Distributed computing

  Edge computing plays a key role in providing ser-vices for emerging compute-intensive applications while bringing computation close to end devices. FPGAs have been deployed to provide custom acceleration services due to their reconfigurability and support for multi-tenancy in sharing the computing resource. This paper explores an FPGA-based Multi-Accelerator Edge Computing System, that serves various DNN applications from multiple end devices simultaneously. To dynamically maximize the responsiveness to end devices, we propose a system framework that exploits the characteristic of applications in patterns and employs a staggering module coupled with a mixed offline/online multi-queue scheduling method to alleviate resource contention, and uncertain delay caused by network delay variation. Our evaluation shows the framework can significantly improve responsiveness and robustness in serving multiple end devices.

  PublisherDOI

• Dynamic Sharing in Multi-accelerators of Neural Networks on an FPGA Edge Device

  2020 · 16 citations

  Senior authorCorresponding
  • Computer Science
  • Computer Science
  • Artificial Intelligence

  Edge computing can potentially provide abundant processing resources for compute-intensive applications while bringing services close to end devices. With the increasing demands for computing acceleration at the edge, FPGAs have been deployed to provide custom deep neural network accelerators. This paper explores a DNN accelerator sharing system at the edge FPGA device, that serves various DNN applications from multiple end devices simultaneously. The proposed SharedDNN/PlanAhead policy exploits the regularity among requests for various DNN accelerators and determines which accelerator to allocate for each request and in what order to respond to the requests that achieve maximum responsiveness for a queue of acceleration requests. Our results show overall 2. 20x performance gain at best and utilization improvement by reducing up to 27% of DNN library usage while staying within the requests’ requirements and resource constraints.

  PublisherDOI

• UltraShare: FPGA-based Dynamic Accelerator Sharing and Allocation

  2019-12-01 · 5 citations

  article

  Despite all the available commercial and open-source frameworks to ease deploying FPGAs in accelerating applications, the current schemes fail to support sharing multiple accelerators among various applications. There are three main features that an accelerator sharing scheme requires to support: exploiting dynamic parallelism of multiple accelerators, sharing accelerators among multiple applications, and providing a nonblocking congestion-free environment for multiple applications to call multiple accelerators. In this paper, we developed a scalable fully functional hardware controller, called UltraShare, with a supporting software stack that provides a dynamic accelerator sharing scheme through an accelerators grouping mechanism. UltraShare allows software applications to fully utilize FPGA accelerators in a non-blocking congestion-free environment. Our experimental results for a simple scenario of a combination of three streaming accelerators invocation show an improvement of up to 8x in throughput of the accelerators by removing accelerators idle times.

  PublisherDOI

• CPSアプリケーションにおける分散タスクチェーンの通信計算共設計【JST・京大機械翻訳】

  IEEE Conference Proceedings · 2019-01-01

  article
  Publisher

• UltraShare: FPGA-based Dynamic Accelerator Sharing and Allocation

  arXiv (Cornell University) · 2019-10-01 · 1 citations

  preprintOpen access

  Despite all the available commercial and open-source frameworks to ease deploying FPGAs in accelerating applications, the current schemes fail to support sharing multiple accelerators among various applications. There are three main features that an accelerator sharing scheme requires to support: exploiting dynamic parallelism of multiple accelerators for a single application, sharing accelerators among multiple applications, and providing a non-blocking congestion-free environment for applications to invoke the accelerators. In this paper, we developed a scalable fully functional hardware controller, called UltraShare, with a supporting software stack that provides a dynamic accelerator sharing scheme through an accelerators grouping mechanism. UltraShare allows software applications to fully utilize FPGA accelerators in a non-blocking congestion-free environment. Our experimental results for a simple scenario of a combination of three streaming accelerators invocation show an improvement of up to 8x in throughput of the accelerators by removing accelerators idle times.

  PublisherOA PDFDOI

• Communication-Computation co-Design of Decentralized Task Chain in CPS Applications

  2019-03-01

  article

  In this paper, we present a method to find an optimal trade-off between computation and communication of decentralized linear task chain running on a network of mobile agents. Task replication has been deployed to reduce the data links among highly correlated nodes in communication networks. The primary goal is to reduce or remove the data links at the cost of increase in computational load at each node. However, with increase in complexity of applications and computation load on end devices with limited resources, the computational load is not negligible. Our proposed selective task replication enables communication-computation trade-off in decentralized task chains and minimizes the overall local computation overhead while keeping the critical path delay under a threshold delay. We applied our approach to decentralized Unscented Kalman Filter (UKF) for state estimation in cooperative localization of mobile multi-robot systems. We demonstrate and evaluate our proposed method on a network of 15 Raspberry Pi3B connected via WiFi. Our experimental results show that, using the proposed method, the prediction step of decentralized UKF is faster by 15%, and for the same threshold delay, the overall computation overhead is reduced by 2.41 times, compared to task replication without resource constraint.

  PublisherDOI

Recent grants

• CAREER: System Synthesis for Self-adaptive Reconfigurable Embedded Systems

  NSF · $400k · 2009–2016

Frequent coauthors

• Majid Sarrafzadeh

  13 shared

• Ryan Kastner

  University of California, San Diego

  13 shared

• Nga Dang

  Radboud University Nijmegen

  10 shared

• Shahin Golshan

  University of California, Irvine

  9 shared

• Love Singhal

  Intel (United Kingdom)

  8 shared

• Hessam Kooti

  Google (United States)

  8 shared

• Nikil Dutt

  6 shared

• Siavash Rezaei

  5 shared

Education

• Ph.D., Computer Science

  University of California, Irvine

  2004

• M.S., Computer Science

  University of California, Irvine

  2000

• B.S., Computer Engineering

  Sharif University of Technology

  1996