About

Erik Brunvand is a professor at the Kahlert School of Computing at the University of Utah. His research interests include computer architecture, specifically accelerators and VLSI, high-performance computing with a focus on accelerators and VLSI, and visual computing, particularly computer graphics. He is associated with the University of Utah, which was one of the first four independent network nodes of the internet, with the first successful transmission occurring on October 29, 1969. Brunvand's work contributes to advancing understanding and development in these areas of computing technology.

Research topics

• Computer Science
• Embedded system
• Parallel computing
• Artificial Intelligence
• Theoretical computer science
• Electrical engineering
• Computer hardware
• Mathematics
• Computer engineering
• Algorithm
• Operating system
• Engineering

Selected publications

• Algorithmic Arts: Attracting a New Type of Student to Computing - The Algorithm is the Medium

  2026-02-13

  articleOpen access1st authorCorresponding
  PublisherDOI

• Algorithmic Arts Degree Programs: A Report on Current Curricular Trends & Pathways for Implementation

  2026-02-13

  articleOpen access1st authorCorresponding
  PublisherDOI

• Semiconductor Microelectronics and Nanoelectronics Research and Education in Academia

  IEEE Design and Test · 2025-11-18

  articleSenior author

  For the last several decades, the Computer and Information Sciences (CISE) Directorate of the National Science Foundation has been a major funding source for basic academic research on design and design automation of micro- and nano-electronic circuits and systems. While this activity started at the very beginning of Mead–Conway VLSI revolution in the late1980s and primarily involved silicon CMOS technologies at the time, more recently emerging non-silicon technologies and their integration in silicon platform have been considered as well. A related organization is the IEEE Council on Electronic Design Automation (CEDA). CEDA was established to foster design automation of electronic circuits and systems at all levels. The Council’s field of interest spans the theory, implementation, and use of EDA/CAD tools to design integrated electronic circuits and systems. This includes tools that automate all levels of the design, analysis, and verification of hardware and embedded software up to and including complete working systems.The last couple of years have seen a renewed interest in the research community triggered by a number of societal reasons, primarily the disruption of supply chain caused by the covid pandemic (see, e.g.,[1]) and the subsequent announcement of the Chips and Science Act [2] by the US government that spurred a flurry of several activities both in the public and private sectors.

  PublisherDOI

• Arches: A Cycle‐Level Hardware Simulation Framework for Exploring Massively Parallel Ray Tracing Architectures

  Computer Graphics Forum · 2025-10-21

  article

  Abstract We introduce Arches, a hardware simulation framework designed to explore and evaluate massively parallel ray‐tracing architectures. Operating at the cycle level, Arches captures detailed performance metrics, including computational throughput, on‐chip data movement across processors, caches, and off‐chip communication via an accurate memory system model. The framework is modular, allowing flexible configuration and interconnection of processor cores, caches, and custom hardware units, enabling easy exploration of diverse hardware architectures. Arches supports high‐performance parallel execution, simulating complex ray tracing workloads to image completion. It leverages the GNU toolchain, allowing users to write C++ software targeting both the simulated architecture and native execution for debugging, including support for custom instructions to control specialized hardware components. The framework provides comprehensive performance instrumentation, offering insights into time‐varying statistics across all modules and identifying performance bottlenecks. Our evaluations demonstrate that Arches delivers performance estimates closely matching real hardware, offering faster and more accurate simulations than existing open‐source hardware simulators. Its modularity also makes it a valuable tool for exploring alternative parallel computing strategies for high‐performance ray tracing, and its extensibility enables adaptation for other workloads or general‐purpose computation.

  PublisherDOI

• NSF Integrated Circuit Research, Education and Workforce Development Workshop Final Report

  arXiv (Cornell University) · 2023-11-03

  preprintOpen access

  As the pace of progress that has followed Moore's law continues to diminish, it is critical that the US support Integrated Circuit (IC or chip) education and research to maintain technological innovation. Furthermore, US economic independence, security, and future international standing rely on having on-shore IC design capabilities. New devices with disparate technologies, improved design software toolchains and methodologies, and technologies to integrate heterogeneous systems will be needed to advance IC design capabilities. This will require rethinking both how we teach design to address the new complexity and how we inspire student interest in a hardware systems career path. The main recommendation of this workshop is that accessibility is the key issue. To this end, a National Chip Design Center (NCDC) should be established to further research and education by partnering academics and industry to train our future workforce. This should not be limited to R1 universities, but should also include R2, community college, minority serving institutions (MSI), and K-12 institutions to have the broadest effect. The NCDC should support the access, development, and maintenance of open design tools, tool flows, design kits, design components, and educational materials. Open-source options should be emphasized wherever possible to maximize accessibility. The NCDC should also provide access and support for chip fabrication, packaging and testing for both research and educational purposes.

  PublisherOA PDFDOI

• LED Paper: Physical Computing with Handmade Paper

  2021-08-09 · 1 citations

  article1st authorCorresponding

  Physical computing involves using embedded computing to interact with the physical world. It’s a core technology for interactive computing. This assignment introduces physical computing through the incorporation of LEDs into handmade paper to make an interactive, visual, and physical artifact.

  PublisherDOI

• Navigating the Seismic Shift of Post-Moore Computer Systems Design

  IEEE Micro · 2021 · 3 citations

  • Computer Science
  • Computer Science
  • Electrical engineering

  Reports on the history and development of computer aided design systems. In quick succession between 1964 and 1971, our field saw the proposal of Moore’s law,1 the coining of the term “computer architecture,”2 and the introduction of the first microprocessor.3 For much of the five decades since then, we have benefitted extraordinarily from both the dynamism of Moore’s law transistor scaling and the stable durability of the hardware–software abstractions of computer architecture. The dynamic duo of Moore’s law and computer architecture have allowed massive scaling to occur, and also to be navigated smoothly with relatively little software impact. For example, in the late 1980s and early 1990s, surges in power density occurred as we reached challenging limits in very large scale integration (VLSI) designs based on bipolar transistors; a technology transition from bipolar to complementary metal–oxide–semiconductor (CMOS) occurred with relatively little impact or awareness from the software portion of the computing community.4 Over the past 10–15 years however, more fundamental shifts have occurred. For example, Dennard scaling,5 a companion phenomenon to Moore’s law stating that power density could remain stable while transistor sizes shrank, is reaching physical limits. This means that further Moore’s law increases in transistor counts are becoming more complex and are only achieved with great effort and at higher power-density costs. Furthermore, as we reach fundamental physical limits in the functioning of small semiconductor transistors, Moore’s law itself is being challenged by the increased physical effort and financial expense required to maintain transistor scaling trends.

  PublisherOA PDFDOI

• <i>Collective Currents</i>: Exploring Sustainability through a Collaborative and Interactive Installation

  Leonardo · 2020-02-27 · 1 citations

  article1st authorCorresponding

  Abstract Water issues in the western United States include a long history of struggle, controversy and politics. Collaboration and compromise are required to achieve desirable outcomes in water quality and water rights. Collective Currents is an interactive art installation, developed collaboratively by a computer engineer and a multimedia artist, that explores the idea of cooperative experience in both literal and conceptual ways and creates an environment that makes reference to and engages the viewer to think about our ability to understand and solve environmental issues, specifically water quality and conservation, through collaboration.

  PublisherDOI

• Mach-RT: A Many Chip Architecture for High Performance Ray Tracing

  IEEE Transactions on Visualization and Computer Graphics · 2020 · 11 citations

  • Computer Science
  • Computer Science
  • Parallel computing

  Data movement, particularly access to the main memory, has been the bottleneck of most computing problems. Ray tracing is no exception. We propose an unconventional solution that combines a ray ordering scheme that minimizes access to the scene data with a large on-chip buffer acting as near-compute storage that is spread over multiple chips. We demonstrate the effectiveness of our approach by introducing Mach-RT (Many chip - Ray Tracing), a new hardware architecture for accelerating ray tracing. Extending the concept of dual streaming, we optimize the main memory accesses to a level that allows the same memory system to service multiple processor chips at the same time. While a multiple chip solution might seem to imply increased energy consumption as well, because of the reduced memory traffic we are able to demonstrate, performance increases while maintaining reasonable energy usage compared to academic and commercial architectures. This article extends our previous work E. Vasiou, K. Shkurko, E. Brunvand, and C. Yuksel, "Mach-RT: A many chip architecture for high-performance ray tracing," in Proc. High-Perform. Graph. Conf., 2019 with design space exploration of the L3 cache size, more detailed evaluation of energy and memory performance, a discussion of energy delay product, and a brief exploration of boards with 16 chips. We also introduce new treelet enqueueing logic for the predictive scheduler.

  PublisherDOI

• Hardware-Accelerated Dual-Split Trees

  Proceedings of the ACM on Computer Graphics and Interactive Techniques · 2020 · 7 citations

  Senior authorCorresponding
  • Computer Science
  • Computer Science
  • Parallel computing

  Bounding volume hierarchies (BVH) are the most widely used acceleration structures for ray tracing due to their high construction and traversal performance. However, the bounding planes shared between parent and children bounding boxes is an inherent storage redundancy that limits further improvement in performance due to the memory cost of reading these redundant planes. Dual-split trees can create identical space partitioning as BVHs, but in a compact form using less memory by eliminating the redundancies of the BVH structure representation. This reduction in memory storage and data movement translates to faster ray traversal and better energy efficiency. Yet, the performance benefits of dual-split trees are undermined by the processing required to extract the necessary information from their compact representation. This involves bit manipulations and branching instructions which are inefficient in software. We introduce hardware acceleration for dual-split trees and show that the performance advantages over BVHs are emphasized in a hardware ray tracing context that can take advantage of such acceleration. We provide details on how the operations needed for decoding dual-split tree nodes can be implemented in hardware and present experiments in a number of scenes with different sizes using path tracing. In our experiments, we have observed up to 31% reduction in render time and 38% energy saving using dual-split trees as compared to binary BVHs representing identical space partitioning.

  PublisherDOI

Recent grants

• Hardware Support for Interactive Ray Tracing

  NSF · $505k · 2006–2010

Frequent coauthors

• Jung-Lin Yang

  16 shared

• Daniel Kopta

  University of Utah

  12 shared

• Josef Spjut

  11 shared

• Sung-Min Lin

  9 shared

• Konstantin Shkurko

  8 shared

• A. Khoche

  7 shared

• Cem Yuksel

  University of Utah

  7 shared

• Elena Vasiou

  University of Utah

  5 shared

Education

• Ph.D., Computer Science

  University of California, Berkeley

  1980

• M.S., Computer Science

  University of California, Berkeley

  1976

• B.A., Mathematics

  University of California, Santa Barbara

  1974