About

Hooman Darabi is a Professor of Electrical and Computer Engineering at UCLA Samueli School of Engineering. His research interests include RF, analog, mixed-mode, and digital electronics. He has received numerous awards and recognitions, including the IEEE Fellow in 2014, the International Solid-State Circuits Conference (ISSCC) top contributor in 2023, and multiple best paper awards from the Journal of Solid-State Circuits and ISSCC. Darabi holds a Ph.D. in Electrical Engineering from UCLA, obtained in 1999, and both his M.S. and B.S. degrees from Sharif University in Iran. His notable contributions to the field have been recognized through awards such as the CICC best invited paper award in 2013, the ISSCC Outstanding Student Paper Award in 2012, and the Broadcom Fellow in 2011. He is actively involved in teaching courses related to electrical engineering and maintains a significant presence in research and academic activities at UCLA.

Research topics

• Computer Science
• Electronic engineering
• Engineering
• Telecommunications
• Electrical engineering
• Combinatorics
• Mathematics
• Algorithm
• Physics

Selected publications

• Design Considerations of High- Frequency-Reference Fractional- N PLL: Architecture and Nonidealities

  IEEE Journal of Solid-State Circuits · 2025-03-21 · 3 citations

  article

  This work presents two calibration-free 7-nm phase-locked loop (PLL) prototypes with high-frequency reference (high-ref): a 240-MHz-driven conventional <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">xor</small>-phase-detector-based PLL and a 2285-MHz-driven harmonic-mixing (HM) PLL, achieving FoMs of −258 and −261 dB, respectively. A frequency-domain analysis of the phase detector’s (PD’s) linearity and gain validates the <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">xor</small> PD as an optimal choice for high-ref PLL architectures. In addition, a first-order pulse-position modulation (PPM) noise model, which arises in high-ref PLLs, is incorporated into Perrott’s existing delta-sigma modulator (DSM) noise model, providing guidance on the choice of reference frequency in high-ref PLL architectures.

  PublisherDOI

• A Calibration-Free Fractional-<i>N</i> Analog PLL With Negligible DSM Quantization Noise

  IEEE Journal of Solid-State Circuits · 2023-04-06 · 12 citations

  article

  An analog fractional-N phase-locked loop (PLL) is presented, which largely eliminates quantization noise by overclocking the delta–sigma modulator (DSM). The overclocking technique, enabled by a multipath phase detector and linear resistor-DAC (RDAC) recombination, does not require a high-reference frequency and does not require calibration. A low-power 7-nm prototype operating at 4.884 GHz exhibits 154-fs rms jitter and a figure of merit (FOM) of 255.8 dB.

  PublisherDOI

• Second-Order Transimpedance Amplifiers in Mixer-First Receivers: Design for Optimum Blocker Tolerance

  IEEE Transactions on Circuits and Systems I Regular Papers · 2023-03-10 · 11 citations

  articleSenior author

  A design-oriented analysis of a transimpedance amplifier (TIA) reveals the optimum compression-free dynamic range for downconverted blockers lying in its 2nd-order transition band. The unique circuit topology is chosen to eliminate low-frequency zeros of the transfer function to TIA output with only one OpAmp. Two approaches lead to TIA designs with or without capacitive positive feedback. Both configurations are analyzed and discussed. Simple and accurate design equations allow the component value to be selected straightforwardly. <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\omega _{0}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula> of the two poles are independently controlled. Analytical expressions for out-of-band (OOB) linearity are derived, explaining different distortion mechanisms from both gate and drain voltages of a FET. The FET gate voltage is shown to affect the distortion even if its swing is much lower than the drain voltage swing. The design fully benefits from 2nd-order filtering, yielding optimum blocker tolerance. Power dissipation is limited by the requirements for noise figure and independent pole control. A mixer-first receiver that operates from 1 to 7GHz is realized on 65nm RF-SOI CMOS. It displays +31.1dBm OOB input-referred third-order intercept point (OOB-IIP3), and +11.8dBm OOB blocker 1-dB compression point (B1dB). The TIA consumes 22mW. The prototype verifies the TIA design.

  PublisherDOI

• A Harmonic-Mixing PLL Architecture for Millimeter-Wave Application

  IEEE Journal of Solid-State Circuits · 2022-10-12 · 35 citations

  article

  A low-noise synthesizer design in the millimeter-wave (mm-wave) range is complicated by the invariably large closed-loop gain and the high operation frequency of the voltage-controlled oscillator (VCO). To overcome these challenges, this work proposes a harmonic-mixing synthesizer system with a 188-dB figure-of-merit mm-wave VCO. The synthesizer extends the bandwidth to 5 MHz, thereby suppressing VCO noise. Importantly, DSM is not amplified by the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{\mathrm{ VCO}}/f_{\mathrm{ ref}}$ </tex-math></inline-formula> gain of the system. A prototype employing a 74-MHz reference achieves a −250-dB phase-locked loop (PLL) figure of merit with a measured 88-fs rms jitter.

  PublisherDOI

• Design and Analysis of an Electrical Balance Duplexer With Independent and Concurrent Dual-Band TX-RX Isolation

  IEEE Journal of Solid-State Circuits · 2022 · 19 citations

  • Computer Science
  • Computer Science
  • Mathematics

  An electrical balance duplexer (EBD) supports dual-band TX-RX isolation enabling frequency-division duplexing (FDD) operation at 5-7 GHz for Wi-Fi 6/6E. A programmable balance network in the EBD can balance the antenna impedance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Z_{\text {ANT}}$ </tex-math></inline-formula> ) in the TX channel and RX channel independently and simultaneously. An on-chip passive bandstop filter as a part of the balance network is implemented, achieving sub-2-dB passband insertion loss (IL) and >20-dB stopband rejection with 10% frequency spacing. This filter separates two impedance tuners in the balance network and enables the independent tunability at two bands. A comprehensive and rigorous analysis of general <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LCR</i> two-ports shows the limit of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$s_{21}$ </tex-math></inline-formula> frequency selectivity when built with finite- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula> elements. The analysis guides the filter design, which guarantees the maximum frequency selectivity. The analysis is then extended to <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LCR</i> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${N}$ </tex-math></inline-formula> -ports as the complete analysis. The EBD provides >40-dB isolation in an 80-MHz channel bandwidth in the TX band (5-6 GHz), for any <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Z_{\text {ANT}}(f_{\text {TX}})$ </tex-math></inline-formula> within VSWR = 2, and independently in the RX band (6-7 GHz) when <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q_{\text {ANT}}&lt; 4.3$ </tex-math></inline-formula> . The EBD is designed for ≤4-dB RX IL and ≤3.8-dB TX IL, and it supports +29-dBm TX output. The EBD is implemented in Towerjazz 65-nm RF silicon-on-insulator (SOI) CMOS technology and occupies an area of 2.3 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

  PublisherDOI

• A Sub-100MHz Reference-Driven 25-to-28GHz Fractional-N PLL with −250dB FoM

  2022 IEEE International Solid- State Circuits Conference (ISSCC) · 2022-02-20 · 11 citations

  article

  A mm-wave frequency synthesizer with output >25GHz inevitably faces the problems of a large closed-loop gain <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$f_{\mathsf{VCO}}/f\mathsf{ref}=N$</tex> . Phase noise and spurs on the reference input and from other sources in the loop referred to its input are amplified by <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$N$</tex> A narrow loop bandwidth must be used to limit the resulting jitter. However, now the loop is unable to adequately suppress the oscillator phase noise, leading to a difficult trade-off. At these operating frequencies, the oscillator is inherently noisier since a capacitor bank for digital tuning greatly compromises the overall LC tank quality factor <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(Q)$</tex> . Therefore, for low output jitter, the synthesizer either needs to allocate disproportionately more current to the VCO than at sub-10GHz, use a sub-10GHz VCO with a frequency multiplier [1], or the reference frequency must be raised to > 100MHz [2], [3], which is beyond the range of reliable, widely available crystal oscillators. In this work, we present a synthesizer that uses a harmonic-mixing (HM) PLL [4], [5] to suppress noise amplification and, therefore, allows the use of a loop with a bandwidth >5MHz. Also, we introduce a coupled mm-wave VCO with only one resonant mode that achieves an FoM (VCO) of 188dB at a 1MHz offset. Combining the two, this synthesizer, driven by a standard 74MHz reference clock, consumes <13mW to deliver 25-to-28GHz output with 88fs rms jitter. It reaches an FoM (PLL) of −250dB.

  PublisherDOI

• Affiliation Index

  2021-06-07

  articleOpen access
  PublisherOA PDFDOI

• Envelope-Tracking Supply Modulator with Trellis Search-Based Switching and 160MHz Capability

  2021-04-01 · 3 citations

  articleOpen access

  Envelope tracking (ET) is in wide use to raise the efficiencies of PAs. We report on the realization of a new envelope-tracking supply modulator (ETSM). A hybrid amplifier (HA) is commonly used, which, in effect, partitions the envelope bandwidth into a low and high subband. An efficient switching buck converter tracks the low band that contains most of the load current. In parallel, an op amp with a Class-AB output stage supplies the current in the high band. Feedback on the op amp servos the total current to the envelope waveform extracted from the baseband modulator (Fig. 1).

  PublisherOA PDFDOI

• An FBAR Driven −261dB FOM Fractional-N PLL

  2021 · 21 citations

  • Computer Science
  • Physics
  • Electronic engineering

  A 1mW −261dB FOM PLL with 91fs jitter is presented that combines a low-noise, high-frequency FBAR reference with the unity-gain harmonic-mixing (HM) PLL to minimize reference noise gain and avoid entirely the amplification of sigma-delta modulator quantization noise and fractional spurs, which, in turn, allows for a substantially larger loop bandwidth to suppress the VCO noise and speed settling.

  PublisherDOI

• Reply to Comments on “Architectural Evolution of Integrated M-Phase High-Q Bandpass Filters”

  IEEE Transactions on Circuits and Systems I Regular Papers · 2021-01-01

  article

  We acknowledge that a factor 2 is indeed missing in the second terms of (14)–(16) in <xref ref-type="bibr" rid="ref2" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[2]</xref> . Fortunately, this typo is not propagated throughout the paper as neither of these equations are used in deriving any other equations of the paper.

  PublisherDOI

Frequent coauthors

• David Murphy

  69 shared

• Arya Behzad

  Broadcom (United States)

  46 shared

• Dihang Yang

  Broadcom (United States)

  44 shared

• Reed Parker

  Cornell University

  37 shared

• Ali Hajimiri

  37 shared

• Richard Ruby

  Boston University

  37 shared

• Cédric Dehos

  Commissariat à l'Énergie Atomique et aux Énergies Alternatives

  36 shared

• Craig Ives

  California Institute of Technology

  36 shared

Awards & honors

• International Solid-State Circuits Conference (ISSCC) top co…
• Journal of Solid-State Circuits (JSSC) best Paper Award 2022
• IEEE Fellow 2014
• Custom Integrated Circuits Conference (CICC) best invited pa…
• Journal of Solid-State Circuits (JSSC) best Paper Award 2012