
About
Joseph R. Cavallaro is a Professor in the Department of Electrical and Computer Engineering at Rice University, where he has been a faculty member since 1988. He also holds a courtesy appointment in the Department of Computer Science and serves as the Director of the Center for Multimedia Communications at Rice. His research focuses on special-purpose VLSI processor architectures, with particular emphasis on their application to signal processing, computer graphics, and robotics. His work involves the development of parallel array architectures optimized for matrix computations, which are fundamental to many numerical algorithms used in wireless communication systems. These algorithms benefit from enhanced parallel architectures and high-speed computer arithmetic, and his research includes studying their efficient implementation on DSP, ASIC, and Application-specific Instruction Processors (ASIP). Dr. Cavallaro holds a Ph.D. in Electrical Engineering from Cornell University, an M.S. from Princeton University, and a B.S. from the University of Pennsylvania. He has been recognized as an IEEE Fellow and has received awards such as the NSF Research Initiation Award and the IEEE Circuits and Systems Society Distinguished Lecture.
Research topics
- Computer Science
- Artificial Intelligence
- Telecommunications
- Computer network
- Operating system
- Algorithm
- Parallel computing
- Database
- Computer architecture
- Mathematics
- Electronic engineering
- Embedded system
- Arithmetic
Selected publications
Outlier Detection Inference Acceleration in a Multi-Tier Wireless Sensor Network
2025-10-26
articleSenior authorAccurate anomaly detection in live data streams while minimizing power consumption and data transmission is a critical objective for low-power embedded systems. This work leverages machine learning techniques, existing wireless communication protocols, and reconfigurable hardware to enable selective data communication and efficient real-time processing. Using the Grand St. Bernard dataset for model training, we developed a network of FPGAs equipped with integrated temperature sensors that communicate with an aggregator node over a wireless network. We introduce a two-tier data reduction framework in which live sensor readings are evaluated using an AE-LSTM prediction model and a custom hardware accelerator to flag deviations from expected behavior. The aggregator FPGA functions as a routing node, facilitating client-server communication, and incorporates a multiprocessing module to manage a CORDIC computation kernel, task scheduling, and anomaly detection. Experimental results demonstrate substantial reductions in data transmission and power consumption, while accurately detecting outliers.
Real-time On-device Inference for ECG Classification of Ventricular Dysfunction
2025-10-26
articleSenior authorWe present the development of a portable embedded system for real-time electrocardiogram (ECG) beat classification for ventricular dysfunction related arrhythmias and conditions. These conditions are clinically relevant for monitoring heart failure patients and possible Left Ventricular Assist Device (LVAD) need, as well as potentially enabling the monitoring of remodeling of the native heart after LVAD implantation. We create a dataset combining single-lead standard datasets from Physionet repository. The system processes single-lead ECG signals using a lightweight, quantized, hardware-accelerated model based on residual connections. We run the proof of concept in an ARM Cortex-M33-based SoC, measuring an inference time of 119 milliseconds with 0.95 mJ of energy consumption at 78 MHz, Flash usage of 709.6KB, and runtime RAM usage of 24.7 KB, with an average AUC of 0.9946 in the multiclass classification task. We validated the system end-to-end using a patient simulator and the MAX30003 sensor. The proposed system enables continuous monitoring without external computation, paving the way towards integration with LVAD systems to allow for patient monitoring.
Journal of the American College of Cardiology · 2025-03-29
articleOpen accessMessage from the Conference Chairs: SiPS 2024
2024-11-04
article1st authorCorrespondingIEEE SiPS 2024 is being held in Boston, Massachusetts at The Engine adjacent to the Massachusetts Institute of Technology. The Engine is a unique startup incubator and accelerator and is an excellent location for the SiPS workshop as the meeting focus is on advanced signal processing architectures and implementations. The 37th IEEE Workshop on Signal Processing Systems (SiPS) is a premier international forum for applied signal processing systems. It addresses all aspects of architecture and design methods of these systems. Emphasis is on current and future challenges in research and development in both academia and industry. We welcome you to The Engine and Boston. You are all part of the 37th SiPS meeting!
IEEE Journal of Biomedical and Health Informatics · 2024-12-02 · 1 citations
articleOpen accessSenior authorWe link the hemodynamic response to inotropic agents with outcomes related to Mechanical Circulatory Support (MCS) by analyzing physiological time series and clinical features using a Machine Learning/Deep Learning ensemble approach for multi-modal waveforms in the pediatric cardiac intensive care setting of a quaternary-care hospital. Unlike existing studies that typically process a single feature type or focus on short-term diagnoses from physiological signals, our novel system processes minute-by-minute multi-sensor data to identify the need for MCS in patients admitted with acute decompensated heart failure. The data used includes tabular clinical features, time series from hemodynamic monitors, and raw waveforms from electrocardiogram and arterial blood pressure signals. Our predictions support an early identification of high-risk patients after just two days of Intensive Care Unit (ICU) admission, with classification and feature importance results confirming the predictive ability of the early hemodynamic response to inotropic agent administration, achieving an AUC of 0.88 in the prediction classification task. This is particularly significant in cases where clinical decisions are not straightforward, such as those in the cohort for this study.
IEEE Circuits and Systems Society Information
IEEE Transactions on Circuits and Systems I Regular Papers · 2024-02-27
articleOpen accessJournal of the American College of Cardiology · 2024-04-01
articleIEEE Circuits and Systems Society Information
IEEE Transactions on Circuits and Systems I Regular Papers · 2024-01-29
articleOpen accessIEEE Circuits and Systems Society Information
IEEE Transactions on Circuits and Systems I Regular Papers · 2023-04-27
articleOpen accessP19: Modeling the Effects of Heartbeat Synchronized Speed Modulation for a Pediatric LVAD
ASAIO Journal · 2023-06-01
articleSenior authorStudy: Increasing the pulsatility of combined LVAD and heart output can be done by modulating the speed of the pump driver in synchrony with the heart rhythm. Increased pulsatility is closer to the physiological norm, lessens blood stagnation, and improves baroreceptor feedback for pressure regulation. This study is a first step to model the systemic response to pump speed modulation to develop the precise synchronization timing and controls for an optimized outcome and to analyze the results. Methods: A previously validated computational model of a mock circulatory loop is used as a platform to observe the hemodynamic effects of synchronized pump speed modulation on the heart. A model of a brushless DC motor used to drive the pediatric LVAD is established using the speed, torque, and inertia constants of the manufacturer specification sheet to represent the motor’s ability to change speed. The pressure and flow HQ curve of the LVAD impeller is used to calculate the pump output flow at different pressures and impeller speeds. The flow of the set speed LVAD is 3L/min, and the flow of the speed modulated LVAD varies between 1 L/min and 5 L/min at diastole and systole respectively. A PID controller is used to control the pump speed to reach the desired flow output. Results: The modulated LVAD flow results in larger changes in aortic pressure. The speed modulated LVAD had an aortic pressure difference of 20 mmHg between the minimum diastole and maximum systole values while the set speed LVAD had a difference of 7 mmHg. The set speed LVAD and the speed modulated LVAD had similar average aortic pressure values of 93mmHg and 91mmHg respectively. The changes in aortic pressure at systole and diastole resulting from the speed modulated flow show that synchronized motor speed modulation results in physiologic conditions closer to the norm.Figure 1. Overview of the Mock Circulatory Loop model and LVAD motor speed controller.Figure 2. Left Ventricular and Aortic Pressure with a set speed LVAD and a speed modulated LVAD.
Recent grants
NSF · $150k · 2013–2016
Unifying Application Specific Processors for Communication Systems
NSF · $218k · 2006–2010
NSF · $392k · 2012–2016
NSF · $274k · 2017–2021
MRI: Development of a National University Wireless Testbed: Rice Configurable Baseband Architecture
NSF · $401k · 2003–2007
Frequent coauthors
- 349 shared
Amara Amara
Beihang University
- 349 shared
Yong Lian
University of Calgary
- 349 shared
Guoxing Wang
Shanghai Jiao Tong University
- 333 shared
Yen-Kuang Chen
- 332 shared
Manuel Delgado‐Restituto
- 332 shared
Alon Ascoli
Polytechnic University of Turin
- 332 shared
N Neihart
IEEE Computer Society
- 317 shared
Mohamad Sawan
Polytechnique Montréal
Labs
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Awards & honors
- 2015 IEEE Fellow
- 2012-2013 IEEE Circuits and Systems Society Distinguished Le…
- 1989-1992 NSF Research Initiation Award
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