Loai Salem
· Assistant ProfessorVerifiedUniversity of California, Santa Barbara · Electrical and Computer Engineering
Active 2000–2025
About
Loai Salem is an Assistant Professor in the Department of Electrical and Computer Engineering at UC Santa Barbara. His research interests include power management integrated circuits, energy harvesters, RF supply modulators, RF power amplifiers, and low-power mixed-signal circuits with a focus on new architectures for analog and digital circuits. He is associated with the Miniaturized Power Electronics and Microsystems Lab, where he conducts research on advanced power electronics and microsystems. His work aims to develop innovative solutions in power management and integrated circuit design, contributing to the advancement of energy-efficient electronic systems.
Research topics
- Computer Science
- Physics
- Engineering
- Electrical engineering
- Electronic engineering
- Optics
- Telecommunications
- Arithmetic
- Quantum mechanics
- Mathematics
- Biology
Selected publications
Realizing AC/RF Transformers from DC-to-DC Voltage Converters Using N-Path Passive Mixers
2025-02-25
article1st authorCorrespondingIn this paper, a new class of transformers is introduced, where the cyclical switching of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{N}$</tex> identical dc-to-dc converters into the signal path at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{f}_{\mathbf{LO}}$</tex> using an N-path passive mixer makes a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{k}:\mathbf{m}$</tex> switched-capacitor (SC) dc-to-dc converter appear as a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{k}:\mathbf{m}$</tex> RF transformer to input RF signals. The cyclical switching of the N k <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$:\mathbf{m}$</tex> SC dc-to-dc converters up-converts their transfer function to the RF frequency of the input LO. The <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{k}:\mathbf{m}$</tex> N-path transformer provides a voltage (current) conversion ratio of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{k}:\mathbf{m}$</tex> (resp. <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{m}:\mathbf{k}$</tex>) between its two ports, and hence, offers an impedance transformation capability of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{k}^{\mathbf{2}}:\mathbf{m}^{\mathbf{2}}$</tex> around a tunable center frequency, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{f}_{\mathbf{LO}}$</tex>. Additionally, the SC transformer provides a tunable high-selectivity filtering capability of a center frequency at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{f}_{\mathbf{LO}}$</tex>. Simulation results of a 65-nm CMOS 1:3 design verify the performance advantages of the proposed SC transformer. With a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{450}-\mathbf{\Omega}$</tex> load attached to the output port and a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{50}-\mathbf{\Omega}$</tex> input (1:9 impedance transformation ratio), the 1:3 8-path transformer design achieves input and output matching across a tuning range from 0.1 to 1 GHz, where <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{S}_{\mathbf{11}}$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{S}_{\mathbf{22}}$</tex> are less than <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$-15\ \mathbf{dB}$</tex> across the range. When both input and output ports are terminated in matched loads, the transformer exhibits almost identical <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{S}_{\mathbf{21}}$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{S}_{\mathbf{12}}$</tex> performance. The insertion loss of the SC transformer is below <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2.75\ \mathbf{dB}$</tex> over the tuning range. The SC transformer design achieves a noise figure below <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4.2\ \mathbf{dB}$</tex> throughout the 0.1-to-1 GHz range and obtains an IIP3 of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$+\mathbf{13.6}\ \mathbf{dBm}$</tex> when <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{f}_{\mathbf{LO}}$</tex> is set to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{500}\mathbf{MHz}$</tex>. The power consumption of the design is below <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4.79\ \mathbf{mW}$</tex>.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2025-06-11 · 3 citations
articleSenior authorThis article introduces a fourth-order <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{m}$</tex-math> </inline-formula>-C low-pass filter for ECG detection that achieves high linearity despite operating under a 0.5 V supply by 1) placing the differential pairs (DPs) of the employed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{m}$</tex-math> </inline-formula> stages in a two-loop feedback structure, 2) employing body-driven rather than gate-driven <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{m}$</tex-math> </inline-formula> DPs, and 3) using current mirrors in place of cascoded transistors in a conventional <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{m}$</tex-math> </inline-formula> stage. Measurement results of a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18~\mu $</tex-math> </inline-formula>m CMOS prototype show that the proposed filter, operating with a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\text {DD}}$</tex-math> </inline-formula> of 0.5 V, achieves an third-order harmonic distortion (HD3) below −40 dB for input amplitudes up to 340 mV<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub>. With an integrated noise of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$154.7~\mu $</tex-math> </inline-formula>V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> over a 240-Hz bandwidth, the filter exhibits a dynamic range (DR) of 53.6 dB, which is competitive with previously reported works.
Impedance Modeling of Switched-Inductor Bias-Flip Piezoelectric Energy Harvesting Circuits
2025-05-25
article1st authorCorrespondingThis paper evaluates the equivalent input impedance, Z<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</inf>, that a parallel synchronized switch harvesting on inductor (P-SSHI) rectifier presents to the internal current, i<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</inf>, of a piezoelectric transducer. Unlike prior impedance modeling work, the charge balance principle is used in this paper to break down Z<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</inf> under a P-SSHI circuit into three shunt components that are independent of each other and solely determined by the internal capacitance, C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</inf>, and resistance, R<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</inf>, of a piezoelectric transducer, as well as the rectifier’s dc load resistance, R<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</inf>, respectively. By isolating the part of Z<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</inf> that relies on C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</inf>, the proposed modeling can quantify the enhancement that a P-SSHI interface circuit provides to the equivalent impedance of C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</inf>, and hence, the improvement to the piezoelectric transducer output power. This approach facilitates performance comparison between a P-SSHI and other piezoelectric interface circuits in terms of the improvement an interface provides to the equivalent impedance of the transducer’s internal capacitance, C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</inf>, independent of the transducer’s internal current, i<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</inf>, which typically varies with the amount of power extracted in transducers of high electromechanical coupling. Another advantage of breaking down Z<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</inf> into three independent shunt components is that the optimal dc load resistance, ${R_L}^{\ast}$, that maximizes the output power of a P-SSHI interface circuit can be directly found from Z<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</inf>. The developed models are verified using circuit simulations.
2025-05-25
article1st authorCorrespondingThis paper introduces a resonant ladder topology that can provide non-unit fraction, N:N-1, resonant voltage conversion ratios while eliminating the charge-sharing loss of all flying capacitors in a converter using a single inductor. Instead of connecting the inductor at the output side, which places the switches between the inductor and capacitors and exposes them to high voltage swings, as in prior non-unit fraction resonant converters, the inductor in the proposed topology is arranged in a series tank configuration. Additionally, the suggested converter requires a two-phase switching sequence instead of a multi-phase one to soft charge all existing flying capacitors. Furthermore, the topology does not change the converter’s resonant frequency among the consecutive switching phases. Importantly, the parent SC topology of the proposed resonant converter is the SC ladder topology that achieves the minimum switch V-A stress applicable to all dc-dc converters for a given conversion ratio. The power FETs in the bottom (N–1) half bridges of the proposed ladder converter are operated as diodes to allow efficient continuous output voltage regulation below the native N:N-1 resonant ratio using frequency or duty modulation. Furthermore, to maintain high efficiency across a wide output voltage range, a recursive reconfiguration structure is introduced that enables altering N and the conversion ratio, N:N-1, offering multiple resonant ratios using a single tank-connected inductor without disconnecting a single capacitor or altering the resonant frequency. Circuit simulation results of a 0.18µm design demonstrate the principal advantages of the proposed recursive resonant converter, where greater than 80% efficiency is achieved, with a 95.6% peak value, over an output range from 0.4 to 1.4V under a load current of 6A.
2025-05-25
articleSenior authorThis paper presents an inductively assisted switched-capacitor (L-SC) converter that employs a small inductor to enable continuous voltage conversion above and below the native n:m conversion ratio of a series-parallel SC converter. Unlike buck and flying-capacitor multilevel converters, the employed inductor in the demonstrated converter delivers only a fraction of the load current rather than its entire value, whereas the embedded SC supplies the remaining amount and lowers the voltage swing across the inductor as well as its current ripple. To maintain high efficiency across a wide output voltage range (i.e., 0.5-to-2.5V), a reconfigurable L-SC converter structure is proposed that enables altering the series-parallel SC conversion ratio between three distinct values, 2:1, 3:1, and 3:2, to facilitate five L-SC operating modes (i.e., <3:1,<2:1,>2:1,<3:2, and >3:2). The five modes specifically allow the converter to avoid operation near the native SC ratios via small duty cycles, which otherwise lead to high discharging currents in the flying capacitors and their associated switches, and hence, low conversion efficiency. Simulation results in 0.18µm CMOS demonstrate that the proposed reconfigurable five-ratio series-parallel L-SC topology achieves a 98% peak efficiency while delivering power at a density of 2.55W/mm3 and a peak power density of 10.18W/mm3 with an efficiency of 96.3%.
A 94.7-dB Dynamic Range Fully Passive Switched-Capacitor Low-Pass Filter With Enhanced Selectivity
IEEE Journal of Solid-State Circuits · 2025-02-13 · 1 citations
articleSenior authorIn this article, a passive gain-boosting technique is employed to improve the bandpass gain, input-referred noise, and area usage of a charge-rotation switched-capacitor (CRSC) filter. In addition, a passive feedback network is introduced, creating a sharp transition between the passband and stopband, thereby enhancing noise and linearity performance compared to prior work employing active feedback. Furthermore, the utilization of the pipeline technique raises the sampling frequency to match the clock frequency. The proposed filter is fabricated in 0.18-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m CMOS technology. Operating from 1.8 V, the measured power dissipation of the filter is 1.52 mW. By applying a 250-MHz clock, the cutoff frequency of the filter can be tuned from 428 kHz to 6.75 MHz, while the dc gain is fixed at 1.33 dB under different bandwidth settings. For a 3-dB cutoff frequency of 2.35 MHz, the measured in-band IIP3 and IIP2 are 25 and 56 dBm, while the out-of-band IIP3 and IIP2 are 22.4 and 71.4 dBm, respectively. The input-referred integrated noise over 110 kHz–2.35 MHz is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8.58{\mu }$ </tex-math></inline-formula>Vrms. Compared to prior art, the proposed filter presents competitive noise performance, area usage, and dynamic range (DR).
Symmetric and Multiphase-Interleaved Ladder Bucks for DC Capacitors Elimination
IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2024-04-29 · 2 citations
article1st authorCorrespondingTo improve power density, a symmetric switched-capacitor (SC) ladder buck (SLB) is proposed in this brief that eliminates the fixed ladder in an SC ladder buck (SCLB) by tying the dc nodes in two 180 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> -phase-shifted cells together. Unlike flying capacitor multilevel converters (FCMCs) that minimize the inductor current ripple, the ladder topology within an SCLB splits the inductor current optimally among the ladder switches, such that the overall equivalent output resistance is minimized. M-phase interleaving is proposed in this brief to allow SLB to regain this current splitting capability when operating via duty cycles larger than 0.5. Simulation results of a six-level four-phase design in 180-nm CMOS verify the performance advantages of the proposed topology.
2024-09-09 · 1 citations
articleSenior authorAn inductively assisted SC ladder converter is introduced that employs a small inductor connected to the output side to enable continuous voltage conversion below the native SC converter discrete ratio. The inductor delivers a fraction of the load current rather than its entire value, facilitating the use of a small-size inductor with a large DCR. The fabricated converter in a $0.18 \mu \mathrm{~m}$ process achieves a 93.7% peak efficiency despite employing a small 0402 inductor with a $73.9 \mathrm{~m} \Omega$ DCR.
2024-05-19 · 2 citations
articleSenior authorThis paper presents a single-inductor resonant switched-capacitor (ReSC) ladder converter for steep N:1 step-down voltage conversion that can employ the same thin-oxide transistors used to implement the end-load digital processing, and hence, can be fully integrated on the same application SoC. By operating the bottom stack of the ReSC switches as diodes, the ReSC converter output voltage can be regulated continuously below the native resonant ratio using frequency or duty modulation while maintaining high efficiency as the converter output voltage is decreased. Simulation results in 0.18μm CMOS demonstrate that the proposed 5:1 ReSC topology achieves a 96.6% peak efficiency while delivering power at a density of 0.16W/mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> and a peak power density of 1.02W/mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> with an efficiency of 85.2%. A 2.3× improvement in the peak power density and 2.8% improvement in the peak-efficiency are achieved compared to the state-of-the-art.
Analysis and Optimization of Sense-and-Set Piezoelectric Energy Harvesting Interface Circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2024-06-20
article1st authorCorrespondingThis article presents the modeling and optimization of a sense-and-set (SaS) rectifier. The basic equations governing the operation of a SaS rectifier are derived analytically using Laplace-transform techniques. An expression for the harvesting efficiency of a SaS rectifier is developed by evaluating the conduction and gate-drive losses as well as the output power of the rectifier. The derived expressions are then employed to locate the optimal design point of a SaS interface circuit. The proposed modeling approach reduces the required run time by more than 2000 times as compared to SPICE simulation without sacrificing accuracy. The following design parameters are determined for maximum efficiency: optimal relative size between the rectifier switches, total conductance of the rectifier, and sensing frequency. The close match between the theoretical expressions and circuit simulation results validates the proposed analysis.
Frequent coauthors
- 16 shared
Patrick P. Mercier
University of California, San Diego
- 8 shared
Sandeep Reddy Kukunuru
University of California, Santa Barbara
- 7 shared
Yehea Ismail
American University in Cairo
- 4 shared
M. Mahmudul Hasan Sajeeb
University of California, Santa Barbara
- 3 shared
Farzan Rezaei
University of California, Santa Barbara
- 3 shared
Rinkle Jain
Intel (United States)
- 3 shared
James F. Buckwalter
University of California, Santa Barbara
- 2 shared
Julian Warchall
University of California, San Diego
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