About

Mohammad Al Faruque joined the Department of Electrical Engineering and Computer Science at UC Irvine in October 2012. Before joining UCI, he was a scientist at Siemens Corporate Research and Technology in Princeton, NJ. He received his B.Sc. degree in Computer Science and Engineering from Bangladesh University of Engineering and Technology (BUET) in 2002, and his M.Sc. and Ph.D. degrees in Computer Science from Aachen Technical University and Karlsruhe Institute of Technology, Germany in 2004 and 2009, respectively. His current research focuses on system-level design of embedded systems and Cyber-Physical-Systems (CPS), with particular interests in CPS design automation, model-based design, multi-core systems, and CPS security. He has received numerous awards including the IEEE CEDA Ernest S. Kuh Early Career Award 2016, the Thomas Alva Edison Patent Award 2016, and several best paper awards. He is involved in research through the Advanced Integrated Cyber-Physical Systems (AICPS) Lab.

Research topics

• Artificial Intelligence
• Computer Science
• Machine Learning
• Computer Security
• Theoretical computer science
• Computer engineering
• Computer network

Selected publications

• HELIOS: Hierarchical Graph Abstraction for Structure-Aware LLM Decompilation

  Open MIND · 2026-01-21

  preprintSenior author

  Large language models (LLMs) have recently been applied to binary decompilation, yet they still treat code as plain text and ignore the graphs that govern program control flow. This limitation often yields syntactically fragile and logically inconsistent output, especially for optimized binaries. This paper presents \textsc{HELIOS}, a framework that reframes LLM-based decompilation as a structured reasoning task. \textsc{HELIOS} summarizes a binary's control flow and function calls into a hierarchical text representation that spells out basic blocks, their successors, and high-level patterns such as loops and conditionals. This representation is supplied to a general-purpose LLM, along with raw decompiler output, optionally combined with a compiler-in-the-loop that returns error messages when the generated code fails to build. On HumanEval-Decompile for \texttt{x86\_64}, \textsc{HELIOS} raises average object file compilability from 45.0\% to 85.2\% for Gemini~2.0 and from 71.4\% to 89.6\% for GPT-4.1~Mini. With compiler feedback, compilability exceeds 94\% and functional correctness improves by up to 5.6 percentage points over text-only prompting. Across six architectures drawn from x86, ARM, and MIPS, \textsc{HELIOS} reduces the spread in functional correctness while keeping syntactic correctness consistently high, all without fine-tuning. These properties make \textsc{HELIOS} a practical building block for reverse engineering workflows in security settings where analysts need recompilable, semantically faithful code across diverse hardware targets.

  DOI

• HELIOS: Hierarchical Graph Abstraction for Structure-Aware LLM Decompilation

  ArXiv.org · 2026-01-21

  articleOpen accessSenior author

  Large language models (LLMs) have recently been applied to binary decompilation, yet they still treat code as plain text and ignore the graphs that govern program control flow. This limitation often yields syntactically fragile and logically inconsistent output, especially for optimized binaries. This paper presents \textsc{HELIOS}, a framework that reframes LLM-based decompilation as a structured reasoning task. \textsc{HELIOS} summarizes a binary's control flow and function calls into a hierarchical text representation that spells out basic blocks, their successors, and high-level patterns such as loops and conditionals. This representation is supplied to a general-purpose LLM, along with raw decompiler output, optionally combined with a compiler-in-the-loop that returns error messages when the generated code fails to build. On HumanEval-Decompile for \texttt{x86\_64}, \textsc{HELIOS} raises average object file compilability from 45.0\% to 85.2\% for Gemini~2.0 and from 71.4\% to 89.6\% for GPT-4.1~Mini. With compiler feedback, compilability exceeds 94\% and functional correctness improves by up to 5.6 percentage points over text-only prompting. Across six architectures drawn from x86, ARM, and MIPS, \textsc{HELIOS} reduces the spread in functional correctness while keeping syntactic correctness consistently high, all without fine-tuning. These properties make \textsc{HELIOS} a practical building block for reverse engineering workflows in security settings where analysts need recompilable, semantically faithful code across diverse hardware targets.

  PublisherOA PDF

• Hyperdimensional Uncertainty Quantification for Multimodal Uncertainty Fusion in Autonomous Vehicles Perception

  ArXiv.org · 2025-03-25 · 1 citations

  preprintOpen accessSenior author

  Uncertainty Quantification (UQ) is crucial for ensuring the reliability of machine learning models deployed in real-world autonomous systems. However, existing approaches typically quantify task-level output prediction uncertainty without considering epistemic uncertainty at the multimodal feature fusion level, leading to sub-optimal outcomes. Additionally, popular uncertainty quantification methods, e.g., Bayesian approximations, remain challenging to deploy in practice due to high computational costs in training and inference. In this paper, we propose HyperDUM, a novel deterministic uncertainty method (DUM) that efficiently quantifies feature-level epistemic uncertainty by leveraging hyperdimensional computing. Our method captures the channel and spatial uncertainties through channel and patch -wise projection and bundling techniques respectively. Multimodal sensor features are then adaptively weighted to mitigate uncertainty propagation and improve feature fusion. Our evaluations show that HyperDUM on average outperforms the state-of-the-art (SOTA) algorithms by up to 2.01%/1.27% in 3D Object Detection and up to 1.29% improvement over baselines in semantic segmentation tasks under various types of uncertainties. Notably, HyperDUM requires 2.36x less Floating Point Operations and up to 38.30x less parameters than SOTA methods, providing an efficient solution for real-world autonomous systems.

  PublisherOA PDFDOI

• Graph Deviation Network for Anomaly Detection and Localization in Additive Manufacturing Systems

  ACM Transactions on Cyber-Physical Systems · 2025-11-18

  articleSenior author

  Additive Manufacturing (AM) has revolutionized industries by enabling the production of complex, customized products with unparalleled efficiency. However, the increasing reliance on AM in critical sectors such as aerospace, healthcare, and defense has exposed it to significant cybersecurity and reliability challenges, including intellectual property theft, process sabotage, and data tampering. These vulnerabilities as well as reliability issues can compromise product integrity, safety, and operational continuity, posing severe risks to both industry and national security. In this work, we propose a novel methodology for modeling the AM process chain as a Cyber-Physical System (CPS) using multi-modal data structured in a graph format. Our methodology leverages Graph Neural Networks (GNNs) to detect and localize anomalies across diverse data modalities, enabling precise identification of both the nature and source of attack/fault. By integrating data fusion, advanced anomaly classification, and localization techniques, our solution provides a robust methodology for enhancing the security and reliability of AM processes, ensuring their safe deployment in critical applications. Furthermore, the proposed technique is adaptable to other industrial systems, underscoring its potential for broader impact in securing critical infrastructure.

  PublisherDOI

• Progress in Weaving Technology in Context of Sustainability

  SDGs and textiles · 2025-01-01

  book-chapter
  PublisherDOI

• LLM4CVE: Enabling Iterative Automated Vulnerability Repair with Large Language Models

  2025-09-10 · 6 citations

  articleSenior author

  Software vulnerabilities remain pervasive, even with the rise of AI-powered code assistants, advanced static analysis tools, and comprehensive testing frameworks. It’s clear that we must move beyond merely preventing these bugs; we need to eliminate them swiftly and efficiently. However, manual code intervention is slow, expensive, and can often introduce new security flaws, especially in legacy codebases. The advent of highly advanced Large Language Models (LLMs) presents a significant opportunity for automated software defect patching. We introduce LLM4CVE, an LLM-based iterative pipeline designed for robust and accurate repair of vulnerable functions in real-world code. We evaluate our pipeline using State-of-the-Art LLMs, including GPT-3.5, GPT-4o, Llama 3 8B, and Llama 3 70B. Our results demonstrate a human-verified quality score of 8.51/10 and a 20% increase in ground-truth code similarity with Llama 3 70B. To foster further research in LLM-based vulnerability repair, we release our evaluation framework, fine-tuned model weights, and experimental results on our website: https://sites.google.com/view/llm4cve

  PublisherDOI

• Hall Sensor Security, The

  2025-01-01

  book-chapterSenior author
  PublisherDOI

• DART: Distribution-Aware Hardware Trojan Detection

  IEEE Transactions on Information Forensics and Security · 2025-01-01

  articleOpen accessSenior author

  Machine Learning (ML) has proven effective in Integrated Circuits (IC) security, particularly in Hardware Trojan (HT) detection. However, a model’s generalization potential depends on its ability to address distribution shifts (DS) in unseen data. Mitigating DS enhances a model’s adaptability to novel variations and threats within the dynamic realm of IC designs and HTs. We formulate HT detection as a DS problem, introducing <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DART</i>, a novel <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Distribution-Aware</i> HT detection framework, to enhance model generalization. Applying <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DART</i> on state-of-the-art Graph Neural Network architecture yields up to 22.96% and 17.37% F1-score improvements for unseen IC designs diverging significantly from the training data.

  PublisherOA PDFDOI

• Collaborative Task Allocation for Heterogeneous Multi-Robot Systems Through Iterative Clustering

  IEEE Robotics and Automation Letters · 2025-11-12 · 1 citations

  article

  Multi-robot systems face the challenge of efficiently allocating teams of heterogeneous robots to tasks. The task allocation problem is complicated by collaborative interactions between robots where teams of robots develop emergent capabilities that enable them to complete tasks that would be inefficient or impossible for individual robots. To address these challenges, we present an iterative clustering algorithm for collaborative task allocation in heterogeneous multi-robot systems. This approach partitions the computationally intractable global optimization problem into smaller, tractable subproblems by iteratively forming clusters of robots and tasks, then optimizing assignments within each cluster. By ensuring robots remain clustered with their currently assigned tasks, we guarantee monotonic improvement in overall utility with each iteration. We analyze the convergence of the algorithm and characterize how cluster size constraints determine which suboptimal assignments could trap the algorithm. In simulation, iterative clustering consistently outperforms simulated annealing, and a group-based auction in both computation time and solution quality, and outperforms a hedonic game approach in solution quality.

  PublisherDOI

• Performance Implications of Multi-Chiplet Neural Processing Units on Autonomous Driving Perception

  2025-03-31 · 1 citations

  articleSenior author

  We study the application of emerging chiplet-based Neural Processing Units to accelerate vehicular AI perception workloads in constrained automotive settings. The motivation stems from how chiplets technology is becoming integral to emerging vehicular architectures, providing a cost-effective tradeoff between performance, modularity, and customization; and from perception models being the most computationally demanding workloads in a autonomous driving system. Using the Tesla Autopilot perception pipeline as a case study, we first breakdown its constituent models and profile their performance on different chiplet accelerators. From the insights, we propose a novel scheduling strategy to efficiently deploy perception workloads on multi-chip AI accelerators. Our experiments using a standard DNN performance simulator, MAESTRO, show our approach realizes 82% and 2.8 × increase in throughput and processing engines utilization compared to monolithic accelerator designs.

  PublisherDOI

Recent grants

• CPS: TTP Option: Medium: Collaborative Research: Low-Cost, High-Throughput, Cyber-Physical Synthesis of Encrypted DNA

  NSF · $358k · 2017–2022

• EAGER: Cybermanufacturing: Defending Side Channel Attacks in Cyber-Physical Additive Layer Manufacturing Systems

  NSF · $200k · 2015–2018

• SHF: Small: A Design Automation Methodology for Flexible Real-Time Computing based on Split and Early Exit Neural Models

  NSF · $500k · 2022–2027

• EAGER: SARE: In-Sensor Hardware-Software Co-design Methodology of the Hall Effect Sensors to Prevent and Contain the EMI Spoofing Attacks in the Analog-RF Systems

  NSF · $300k · 2020–2024

Frequent coauthors

• Sujit Rokka Chhetri

  Palo Alto Networks (United States)

  34 shared

• Arquimedes Canedo

  Siemens (United States)

  33 shared

• Shih-Yuan Yu

  University of California, Irvine

  31 shared

• Mohanad Odema

  28 shared

• Arnav Vaibhav Malawade

  University of California, Irvine

  25 shared

• Nafiul Rashid

  Research!America (United States)

  23 shared

• Rozhin Yasaei

  20 shared

• Korosh Vatanparvar

  Samsung (United States)

  19 shared

Awards & honors

• IEEE CEDA Ernest S. Kuh Early Career Award 2016
• Thomas Alva Edison Patent Award 2016
• 2016 DATE Best Paper Award
• 2015 DAC Best Paper Award
• 2009 ICCAD Best Paper Award