About

Ray Klefstad is an Associate Professor of Teaching in the Department of Computer Science at UC Irvine's Donald Bren School of Information & Computer Sciences. He has served as a full-time lecturer, assistant adjunct professor, and researcher at UCI for more than 20 years. Klefstad was recently recognized as UCI’s 2017 Lecturer of the Year before advancing to his current position in September 2017. His research areas include compilers, operating systems, distributed computing, real-time computing, embedded systems, middleware, object-oriented design, design patterns, and object-oriented programming languages. He is also involved in developing learning and teaching tools for information and computer sciences.

Research topics

• Computer Science
• Artificial Intelligence
• Multimedia
• Mathematics education
• Psychology
• Programming language

Selected publications

• Scaling Engagement: Leveraging Social Annotation and AI for Collaborative Code Review in Large CS Courses

  2026-02-13

  articleOpen access1st authorCorresponding

  Peer code review activities, like their industry-proven counterpart code reviews, have had many benefits reported: they enhance programming ability, conceptual understanding, and community, while improving students' debugging ability and code quality. Problems, however, can include lack of engagement and poor review quality; therefore, motivating students to engage with code reviews is essential.

  PublisherDOI

• More A's, Fewer F's in a Data Structures Class in a New Classroom Building Designed for Active Learning

  2020 · 1 citations

  1st authorCorresponding
  • Computer Science
  • Mathematics education
  • Artificial Intelligence

  Recognizing the value of evidence-based active learning teaching methods, as well as the need for higher-order skills in its increasingly diverse student body, the University of California, Irvine recently invested $62 million in a new classroom building designed for active learning. We report first experiences in transforming a Data Structures class to take advantage of this space. The specially designed environment made it easier for students to collaborate on problem solving, discuss their solutions with each other, and share them with the entire class for further discussion. Survey data showed that students appreciated the benefits of the space and the active learning exercises. Compared to a previous offering of the course taught by the same instructor in a traditional lecture hall, students in this highly-structured active learning classroom were more likely to earn an A grade (41% vs 75%), and three times less likely to fail (6.7% vs 2.1%).

  PublisherDOI

• Active Learning with Code Writing in Large Lectures

  2020 · 1 citations

  1st authorCorresponding
  • Computer Science
  • Computer Science
  • Artificial Intelligence

  Studies have found that many CS students perform poorly on basic programming tasks, and interviewers in industry complain that CS graduates cannot write code. Learning gains have been shown from active learning techniques such as Peer Instruction, but only for multiple-choice questions, not for writing code. Studies of multiple choice questions such as code tracing have shown weak correlations to code writing, and extremely small improvements in syntax in only one third of students. These results are consistent with a century of research showing limited transfer of knowledge, and skill acquisition literature showing that skill is developed only with many hours of practice. We developed an active learning activity called LiveQuiz for large university courses, enabling every student to write specific small functions during lecture, using an online community tool on their own devices. Anonymous responses can be seen on the lecture hall screen in a single conversation thread, which the instructor scrolls. Both students and the instructor analyze and discuss the correctness of different solutions. LiveQuiz was effective in helping students to write correct code: e.g, the percentage of correct sequential search functions rose from 36% to 96%. LiveQuiz is a promising active learning technique using existing tools, giving students practice and prompt feedback in a high-level skill. It is fast and easy to implement, and it provides the instructor first drafts of students' problem solving, which can yield insights for future teaching.

  PublisherDOI

• Fast, Interactive Worst-Case Execution Time Analysis With Back-Annotation

  IEEE Transactions on Industrial Informatics · 2012-02-10 · 16 citations

  article

  For hard real-time systems, static code analysis is needed to derive a safe bound on the worst-case execution time (WCET). Virtually all prior work has focused on the accuracy of WCET analysis without regard to the speed of analysis. The resulting algorithms are often too slow to be integrated into the development cycle, requiring WCET analysis to be postponed until a final verification phase. In this paper, we propose interactive WCET analysis as a new method to provide near-instantaneous WCET feedback to the developer during software programming. We show that interactive WCET analysis is feasible using tree-based WCET calculation. The feedback is realized with a plugin for the Java editor jEdit, where the WCET values are back-annotated to the Java source at the statement level. Comparison of this tree-based approach with the implicit path enumeration technique (IPET) shows that tree-based analysis scales better with respect to program size and gives similar WCET values.

  PublisherDOI

• Traffic-aware power optimization for network applications on multicore servers

  2012-05-31 · 6 citations

  articleSenior author

  In this paper, we design, implement, and evaluate a traffic-aware and power-efficient multicore server system by translating incoming traffic rate to appropriate system operating level, which is then translated to optimal per-core frequency configuration. According to the varying traffic rate, the system can adjust the number of active cores and per-core frequency "on-the-fly" via the use of per-core DVFS, power gating, and power migration techniques based on our new power model which considers both dynamic and static power consumption of all cores. Results on an AMD machine with two Quad-Core Opteron 2350 processors for six real network applications chosen from NetBench [19] show that our scheme reduces power consumption by an average of 41.0% compared to running with full capacity without any reduction in throughput. It also consumes less power than three other approaches, chip-wide DVFS [22], power gating [17], and chip-wide DVFS + power gating [15], by 35.2%, 24.3%, and 10.5% respectively.

  PublisherDOI

• Measurement Techniques in a Hybrid Approach for Deriving Tight Execution-time Bounds of Program Segments in Fully-featured Processors

  2008-04-01 · 5 citations

  article

  A hybrid approach to deriving tight execution-time bounds of program segments was proposed very recently. This approach symbiotically combines analytical and measurement-based methods to find a tight execution- time bound falling between the maximum measured execution time and an analytically derived loose bound. It also enables the estimation of the probability of the derived tight bound not being exceeded at run time. This paper provides a refined description of the hybrid approach and presents techniques for measuring the execution times of acyclic-path segments (APSs), which are possible execution sequences of instructions that contain no cycles and the basic units of analysis in the hybrid approach. In this paper, we also report the results of the hybrid approach in the derivation of tight execution-time bounds of three algorithms frequently used in the evaluation of WCET analysis techniques.

  PublisherDOI

• Toward Libraries for Real-Time Java

  2008-05-01 · 6 citations

  articleOpen accessSenior author

  Reusable libraries are problematic for real-time software in Java. Using Java's standard class library, for example, demands meticulous coding and testing to avoid response time spikes and garbage collection. We propose two design requirements for reusable libraries in real-time systems: worst-case execution time (WCET) bounds and worst- case memory consumption bounds. Furthermore, WCET cannot be known if blocking method calls are used. We have applied these requirements to the design of three Java-based prototypes: a set of collection classes, a networking stack, and trigonometric functions. Our prototypes show that reusable libraries can meet these requirements and thus be viable for real-time systems.

  PublisherOA PDFDOI

• Design, implementation and test of a wireless peer-to-peer network for roadway incident exchange

  International Journal of Vehicle Information and Communication Systems · 2008-01-01 · 3 citations

  articleSenior author

  The existing paradigms for vehicular traffic monitoring and control have a strong infrastructure bias. Data collection and processing typically require a support system that may be prohibitively expensive or suffer from scalability issues. Current research aims to solve these problems with local-area wireless technology, allowing the vehicles themselves to form an ad hoc network. Our vision of such a traveller-centric, zero-infrastructure system is called Autonet. In this paper, we present the key Autonet concepts, validated through a prototype implementation and field measurements. In the prototype, an in-vehicle client with an informative GUI continuously listens for other clients, exchanging knowledge about network state once contact is made. We show that knowledge about traffic conditions can be propagated successfully using this system. The prototype also enabled benchmarking of 802.11b wireless technology in a transportation environment. These measurements establish its maximum throughput at approximately 3,500 traffic incidents for two vehicles passing at highway speeds.

  PublisherDOI

• Realistic models for scheduling tasks on network nodes

  2008-01-01 · 1 citations

  article1st authorCorresponding

  Parallel distributed computing has been widely studied and utilized to enable grids (or clusters) to meet the increasing demand of computation, especially in the field of scientific computation and modeling. The goal of distributed computing platforms is to provide the necessary infrastructure so that applications and their users can aggregate resources dynamically and shorten the processing time of the applications. With the rapid development of the Internet, the current distributed computing platforms are becoming more complicated. A typical type of modern distributed computing platforms is grid. Because the modern distributed computing platforms may contain numerous computational network nodes, one important challenge is how to schedule the load of tasks to these network nodes efficiently [1]. In addition, the environments of current computational platforms are becoming more complicated due to the availability of high performance network nodes and interconnects. Therefore, more advanced scheduling algorithms should be utilized to handle these problems. It is therefore necessary to create a new generation of schedulers that provides more comprehensive support for addressing the modern distributed computing platform requirements, so that the network nodes can be utilized effectively By analyzing and identifying the limitations of applying conventional scheduler technologies for distributed parallel applications, this dissertation presents a new design and its associated algorithms for enhancing conventional schedulers to provide better performance with considering more realistic factors. This dissertation also presents both mathematical and empirical analysis of three different proposed models. This dissertation provides three contributions to the field of task scheduling in distributed computing. First, current published algorithms are analyzed and weakness are exposed when real-world factors are considered, such as startup-costs, arbitrary processor times. Second, it contributes to the design of the scheduling algorithms by considering more realistic factors, which extend the usages of schedulers. Finally, it presents empirical and analytical results to demonstrate the effectiveness and the advantage of the proposed algorithms. The work in this dissertation has a broader impact beyond the algorithms in which they were developed, as it provides deeper understanding of scheduling tasks in the more realistic models, which will allow us to design more efficient algorithms.

  Publisher

• A Modular Worst-case Execution Time Analysis Tool for Java Processors

  2008-04-01 · 14 citations

  articleSenior author

  Recent technologies such as the real-time specification for Java promise to bring Java's advantages to real-time systems. While these technologies have made Java more predictable, they lack a crucial element: support for determining the worst-case execution time (WCET). Without knowledge of WCET, the correct temporal behavior of a Java program cannot be guaranteed. Although considerable research has been applied to the theory of WCET analysis, implementations are much less common, particularly for Java. Recognizing this deficiency, we have created an open-source, extensible tool that supports WCET analysis of Java programs. Designed for flexibility, it is built around a plug- in model that allows features to be incorporated as needed. Users can plug in various processor models, loop bound detectors, and WCET analysis algorithms without having to understand or alter the tool's internals.

  PublisherDOI

Recent grants

• Collaborative Research: EHS: Components and Aspects for Embedded Middleware

  NSF · $330k · 2004–2008

Frequent coauthors

• Trevor Harmon

  19 shared

• Juan A. Colmenares

  Microsoft (United States)

  7 shared

• Douglas C. Schmidt

  Vanderbilt University

  5 shared

• Shruti Gorappa

  University of California, Irvine

  5 shared

• Jie Hu

  University of Electronic Science and Technology of China

  5 shared

• Martin Schoeberl

  Technical University of Denmark

  3 shared

• Raimund Kirner

  University of Hertfordshire

  3 shared

• Yue Zhang

  3 shared

Awards & honors

• UCI’s 2017 Lecturer of the Year