About

V.N. Vimal Rao is a Statistician and Educational Psychologist currently affiliated with the Department of Statistics at the University of Illinois in Urbana-Champaign. His main interest lies in the psychology of statistics, specifically exploring what it means to do statistics and how individuals learn to do it. His work encompasses research and teaching in these areas, and he has mentored students in his field. More information about his background, research, and educational contributions can be found on his website, which also details his education and work experience.

Research topics

• Computer Science
• Artificial Intelligence
• Real-time computing
• Electronic engineering
• Algorithm
• Engineering
• Embedded system
• Statistics
• Mathematics

Selected publications

• Statistical Timing Analysis considering Multiple-Input Switching

  2020 · 6 citations

  • Computer Science
  • Computer Science
  • Artificial Intelligence

  Traditional statistical static timing analysis (SSTA) using available single-input switching (SIS) based gate delay libraries either ignore timing impact from multiple-input switching (MIS) or use single-corner (deterministic) models for MIS consideration. This paper presents a method for modeling the impact of MIS on statistical timing accurately using concepts of convolution and chain ruling. Experimental results in a commercial SSTA framework demonstrate negligible run-time overheads of modeling MIS while accurately exposing timing slack optimism in an SIS based flow of up to 17 pico-seconds on designs mapped to a 14 nanometer technology library. Prediction of timing critical paths due to MIS show excellent correlation to silicon hardware. Comparisons with prior work illustrate the accuracy improvements of the presented work.

  PublisherDOI

• Statistical path tracing in timing graphs

  2016-05-25 · 2 citations

  article1st authorCorresponding

  Path tracing is a key requirement in providing various functionalities in a Static Timing Analysis (STA) tool. With growing design sizes and advancements in STA techniques like statistical timing analysis, path tracing techniques need to be more efficient and accurate. Naïve extensions of path tracing techniques for statistical timing analysis are found to be inefficient and inaccurate. In this paper, we present a novel Statistical Path Tracing (SPT) approach and illustrate its application in Common Path Pessimism Removal (CPPR). We demonstrate that SPT is more efficient and accurate when compared to a Deterministic Path Tracing (DPT) approach.

  PublisherDOI

• Transistor-Level Tools for High-End Processor Custom Circuit Design at IBM These complex software tools model transistor operation and can be combined to design, check, verify and optimize systems for specific applications.

  2007-01-01

  article

  IBM's high-performance microprocessor designs leverage internally developed electronic design automation tools to create high-frequency, power efficient, and robust microprocessors. This paper describes some of the tools employed in the custom circuit design methodology in IBM. The tools described include a transistor-level block-based static timer, a static noise analysis methodology, and a transistor width tuner that optimizes performance and area. We also describe the application of electrical rule checking used to enforce consistent design practices. Finally, we discuss a macro extraction tool that determines parasitic resistance and capacitance of interconnect from a layout.

  Publisher

• Partitioning issues in circuit simulation on multiprocessors

  2003-01-06 · 4 citations

  articleSenior author

  A decomposition technique known as node tearing is used to perform circuit simulation on a multiprocessor. The effect of partitioning the circuit on the final speedup achieved is considered. Using a very simple model for the LU decomposition time of sparse matrices, a circuit-partitioning problem based on node tearing is formulated to maximize speedup on a multiprocessor. An abstract hypergraph partitioning problem is then posed along with an algorithm for its solution. The original circuit partitioning problem is then transformed into an equivalent hypergraph partitioning problem, thereby generating partitions for the circuit. The effect of the tradeoff of circuit-partitioning time versus the number of available processors on the speedup factor is also studied.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

  PublisherDOI

• Session details: Delay and noise modeling in the nanometer regime

  2003-06-02

  article1st authorCorresponding

  No abstract available.

  PublisherDOI

• A new eigenvalue bound for reversible Markov chains with applications to the temperature-asymptotics of simulated annealing

  2002-12-04 · 6 citations

  articleSenior author

  A novel upper bound is presented for the second largest eigenvalue of a finite reversible time-homogeneous Markov chain as a function of three parameters, namely the smallest transition probability, the underlying structure of the chain, and the skewness of the equilibrium distribution. Simulated annealing (SA) is an example of a probabilistic algorithm that is widely used for solving combinatorial optimization problems, wherein the transition probabilities are controlled by a certain temperature parameter T>0. Using the results presented, it is possible to bound the time constant of convergence of SA to equilibrium at any fixed temperature T>0, and also to study the temperature asymptotics, namely the growth of this bound as T to 0.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

  PublisherDOI

• A convex optimization approach to transistor sizing for CMOS circuits

  2002-12-10 · 29 citations

  article

  The transistor sizing problem of minimizing the circuit area, subject to the circuit delay being less than a given specification, is formulated as a convex programming problem. An efficient convex programming algorithm is then used to obtain the exact solution. Experimental results on a variety of circuits show that, for a given delay specification this approach is able to produce circuits with significantly smaller area when compared with TILOS.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

  PublisherDOI

• Aggressive crunching of extracted RC netlists

  2002-01-01 · 7 citations

  article1st authorCorresponding

  This paper presents a short-and-update technique for resistors (possibly connected to sinks) that can further crunch the RC network effectively after eliminating internal nodes [1,14]. Our method produces a realizable RC circuit and preserves the total capacitance in the network. While our technique cannot guarantee preserving the Elmore delay at each network sink node, the maximum delay error can be controlled by the user. Our method provides a smooth tradeoff between run time and delay accuracy, ranging from full retention of all resistors to complete elimination.

  PublisherDOI

• iDEAS: a delay estimator and transistor sizing tool for CMOS circuits

  2002-12-04 · 5 citations

  articleSenior author

  The iDEAS algorithm incorporates a delay estimator that uses both the rise and fall delay to find the critical path through a given circuit. A method that attempts to minimize the area-delay product of the circuit is developed to optimize the sizes of transistors along the critical path. These two steps are repeated until the specified delay and area requirements for the circuit are met. This algorithm is designed for use on combinational circuits, and is also applicable to clocked circuits, where each stage of the clocked circuit is combinational.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

  PublisherDOI

• A system for electromigration analysis in VLSI metal patterns

  2002-12-09 · 10 citations

  article

  The authors describe a CAD (computer-aided design) system for reliability analysis of VLSI CMOS circuits, with emphasis on electromigration estimation in power and ground metal lines. The system consists of three main components: extraction of circuit netlist and parameters and RC line models from layout; calculation of expected or average current waveforms drawn by the circuit at the contacts of the buses; and computation of average current densities in sections of the power and ground buses for electromigration estimation. The system tools have been integrated around the Berkeley OCT/VEM design framework system.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

  PublisherDOI

Frequent coauthors

• I.N. Hajj

  University of Illinois Urbana-Champaign

  9 shared

• T.N. Trick

  Urbana University

  8 shared

• D. Overhauser

  6 shared

• Sachin S. Sapatnekar

  6 shared

• Youssef Saab

  University of Missouri

  6 shared

• Madhav P. Desai

  Indian Institute of Technology Bombay

  5 shared

• K.S. Arun

  4 shared

• Pravin M. Vaidya

  Indian Institute of Technology Kharagpur

  3 shared